CP3SP33SMSSLASHNOPB datasheet(31/407 Pages) TI1

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CP3SP33

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SNOSCW5 – MAY 2013

8.1

Bus Arbiter Registers

The bus arbiter registers control and provide status for certain aspects of the bus arbiter. The bus arbiter

registers are listed in Table 8-2.

Table 8-2. Bus Arbiter Registers

NAME

ADDRESS

DESCRIPTION

MASTGP

FF F000h

Master Group Register

ARBALGO

FF F004h

Arbitration Algorithm Register

DFTMAST

FF F008h

Default Master Register

ARBCFGLK

FF F00ch

Arbiter Configuration Lock Register

8.1.1

Master Group Register (MASTGP)

The MASTGP register is a 32-bit, read/write register that selects the priority group for each potential bus

master. After reset, this register is clear.

6 5

4 3

2 1

Reserved

MAS4

MAS3

MAS2

MASn

The Master field selects the priority group for the corresponding potential bus master.

00 – Group A.

01 – Group B.

10 – Group C.

11 – Group D.

8.1.2

Arbitration Algorithm Register (ARBALGO)

The ARBALGO register is a 32-bit, read/write register that selects the arbitration policy used for each

priority group. A ter reset, this register is initialized to 0000 0001h.31

Reserved

GRD

GRC

GRB

GRA

GRn

The Group bit selects the arbitration policy for the corresponding group.

0 – Linear priority based on master number.

1 – Round-robin.

8.1.3

Default Master Register (DFTMAST)

The DFTMAST register is a 32-bit, read/write register that selects the master number of the default bus

master. After reset, this register is initialized to 0000 0002h.

4 3

Reserved

DFTMAST

The Default Master field specifies the master number. There are two defined values:

2h – CPU.

3h – CPU DMA controller.

CPU Core Bus Arbitration

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