CP3SP33SMSSLASHNOPB datasheet(100/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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16.6.2 Entering Idle Mode

Idle mode can only be entered from Power Save mode. Idle mode is entered by writing 1 to the

PMMSTCTL.IDLE bit and then executing a WAIT instruction.

16.6.3 Disabling the High-Frequency Clock

When the low-frequency oscillator is used to generate the Slow Clock, power consumption can be

reduced further in the Power Save or Idle mode by disabling the high-frequency oscillator. This is

accomplished by writing a 1 to the PMMSTCTL.DMC bit before executing the WAIT instruction that puts

the device in the Power Save or Idle mode. The high-frequency clock is turned off only after the device

enters the Power Save or Idle mode.

The CPU operates from Slow Clock in Power Save mode. It can turn off the high-frequency oscillator at

any time by writing a 1 to the PMMSTCTL.DMC bit. The high-frequency oscillator is always enabled in

Active mode and is always disabled in Halt mode, without regard to the PMMSTCTL.DMC bit.

Immediately after power-up and entry into Active mode, software must wait for the low-frequency oscillator

to become stable before it can put the device in Power Save mode. It should monitor the

PMMSR.SCLKSTB bit for this purpose. Once this bit is set, the low-frequency oscillator is stable and

Power Save mode can be entered.

Slow Clock must come from the low-frequency oscillator or an external clock (driven on X2CKI), not

derived from Main Clock, if the high-frequency oscillator will be disabled.

16.6.4 Entering Halt Mode

Halt mode can only be entered from the Active and Power Save modes. In Active mode, the

PMMSTCTL.WBPSM bit must be set before entering Halt mode. Halt mode is entered by writing 1 to the

PMMSTCTL.HALT bit and then executing a WAIT instruction.

16.6.5 Software-Controlled Transition to Active Mode

A transition from Power Save mode to Active mode can be accomplished by either a software method or a

hardware wake-up event. The software method is to write a 0 to the PMMSTCTL.PSM bit. The value of

the register bit changes only after the transition to the Active mode is completed.

If the high-frequency oscillator is disabled for Power Save operation, the oscillator must be enabled and

allowed to stabilize before the transition to Active mode. To enable the high-frequency oscillator, clear the

PMMSTCTL.DMC

bit.

Before

clearing

the

PMMSTCTL.PSM

bit,

software

must

poll

the

PMMSR.MCLKSTB bit to determine when the oscillator has stabilized.

16.6.6 Wake-Up Transition to Active Mode

A hardware wake-up event switches the device directly from Power Save, Idle, or Halt mode to Active

mode. When a wake-up event occurs, the on-chip hardware performs the following steps:

1. Clears the PMMSTCTL.DMC, PMMCSTCTL.DSC, and PMMPLLnCTL2.DPLLC bits, which enable the

high-frequency oscillator, low-frequency oscillator, and PLL Clocks (if any were disabled).

2. Waits for the PMMSR.MCLKSTB and PMMSR.SCLKSTB bits to become set. If either of the PLLs were

enabled before entering the low-power mode, waits for the corresponding

PMMPLLnCTL2.PLLCLKSTB bits to become set.

3. Switches the device into Active mode.

16.6.7 Power Mode Switching Protection

The Power Management Module has several mechanisms to protect the device from malfunctions caused

by missing or unstable clock signals.

100

Power Management Module

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