CP3SP33SMSSLASHNOPB datasheet(44/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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10 External Bus Interface Unit

The External Bus Interface Unit (EBIU) provides a memory bus interface that supports three types of

external memory:

•

Asynchronous RAM

•

Page-Mode Flash Memory

•

ROM

Because the CP3SP33 does not have on-chip non-volatile memory, the EBIU is typically used to add at

least one non-volatile memory device for holding the boot code. The EBIU provides programmable chip

select outputs XCSn for two or three memory devices, depending on package type. The memory type,

base address, width (8, 16, or 32 bits), size, and timing are independently programmable for each of the

memory devices.

The physical address space available on the external bus does not occupy a fixed location in the address

space of the CPU or Teak on-chip 32-bit buses. The location(s) are programmable in the EBIU registers.

The EBIU asserts a chip select to an external memory device when an on-chip bus uses a region of its

address space mapped to an external memory device. There are two regions in the on-chip bus address

space which are available for external devices:

•

0002 0000h to 00FE FFFFh—a 16M-byte space, minus a 128K space at the bottom and a 64K space

at the top

•

0100 0000h to 0FFF FFFFh—a 240M-byte space (256M, minus a 16M space at the bottom)

The EBIU does not relocate the address passed from the on-chip AHB buses to the external bus. The

mapping only affects activation of the chip select signals. Any of the chip selects may be configured for

either of two regions.

10.1 External Bus Signals

There are 6 types of bus signals. The number of signals varies with the package type, as shown in

Table 10-1.

Table 10-1. External Bus Signals

PACKAGE PIN COUNT

NAME

DESCRIPTION

FBGA-224

FBGA-144

XAn

Address Bus

XDn

Data Bus

XWE

Write Enable

XOE

Output Enable

XBEn

Byte Enables

XCSn

Chip Selects

The byte order is little-endian (LSB at lowest address). The EBIU shifts the address to correspond to the

width of the external memory device, so the XA address may be either a byte, word, or doubleword

address. Mixing of memory types is allowed.

10.2 Default Memory Configuration

The default configuration after reset for the external memory devices is shown in Table 10-2. Booting from

an 8-bit external memory is not supported.

The cycle times are quoted in HCLK Clock periods. By default, the HCLK Clock frequency following reset

is the input clock frequency (X1CLKI/X1CLKO or CLKIN) divided by 16.

External Bus Interface Unit

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