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CP3SP33SMS/NOPB Datasheet(PDF) 109 Page - Texas Instruments

Part # CP3SP33SMS/NOPB
Description  Connectivity Processor with Cache, DSP, and Bluetooth짰, USB, and Dual CAN Interfaces
PDF  407 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

CP3SP33SMS/NOPB Datasheet(HTML) 109 Page - Texas Instruments

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CP3SP33
www.ti.com
SNOSCW5 – MAY 2013
18 Input/Output Ports
The CP3SP33 has 64 software-configurable general-purpose I/O pins (36 on the FBGA-144 package),
organized into four ports, named Port E, Port F, Port G, and Port H. All 16 pins on Ports E, F, and G and
three pins on 8-bit Port H have independently programmable MIWU channels, which give them the
capability to interrupt the CPU and wake up the system from low-power modes.
In addition to their general-purpose I/O function, most of the pins on Ports E, F, and G have alternate
functions for use with on-chip peripheral modules such as the UARTs and timers. Architecturally, there
may be two alternate functions for a port pin, and software must specify which function to select (A or B),
even when only one function is implemented. The alternate functions of all I/O pins are shown in
Table 18-2. To avoid glitches, software should first select the alternate function, then enable the alternate
function, and finally initialize the module which uses the alternate function.
The I/O pin characteristics are fully programmable. Each pin can be configured to operate as a TRI-
STATE output, push-pull output, input with weak pullup, input with weak pull-down, or high-impedance
input. Different pins within the same port can be individually configured to operate in different modes.
Figure 18-1 shows the I/O port pin logic. The register bits, multiplexers, and buffers allow the port pin to be
configured into the various operating modes.
To reduce power consumption, input buffers configured for general-purpose I/O are only enabled when
they are read. When configured for an alternate function, the input buffers are enabled continuously. To
minimize power consumption, input signals to enabled buffers must be held within 0.2 volts of the VCC or
GND voltage.
The electrical characteristics and drive capabilities of the input and output buffers are described in
Section 36.
Copyright © 2013, Texas Instruments Incorporated
Input/Output Ports
109
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