CP3SP33SMSSLASHNOPB datasheet(122/407 Pages) TI1

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CP3SP33

SNOSCW5 – MAY 2013

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19.3 LMX5251 Power-Up Sequence

To power-up a Bluetooth system based on the CP3SP33 and LMX5251 devices, the following sequence

must be performed.

1. Apply VDD to the LMX5251.

2. Apply IOVCC and VCC to the CP3SP33.

3. The RESET_N pin of the radio chip is directly connected to the Vuc pin of the radio chip and the

RFVcc pin of the Pulsar. As the voltage on the RESET_N (also Vuc and RFVcc) is applied after

applying a voltage to the Vdd pin, the LMX5251 is properly reset.

4. After (Power-On) reset of the Pulsar the RFDATA pin of the Pulsar is driven high. The RFCE, RFSYNC

and SDAT pins of te Pulsar are set into high-impedance state. However, there are pullup/pulldown

resistors built into the S_CLK, S_DATA, S_LE, and Rx/Tx_Synch pins of the radio chip to assure the

correct initial voltage levels for a proper power-up sequence.

5. The RFDATA pin driven to logic high level causes the radio chip to enable its oscillator and after an

oscillator start-up delay, the radio chip outputs a stable 12 MHz clock (BB_CLK/BRCLK) to the Pulsar.

6. By receiving a stable clock from the radio chip, the Pulsar is operational and the CR16 enables the

alternate function of the GPIO pin, used by the RF interface.

7. Now the Bluetooth LLC can directly control the RF interface pins and sets the pins to the logic high

levels required during the power-up phase. The RFCE pin driven high forces the radio chip to switch

from “power-up” to “normal” mode and to disable it’s internal pullup/pulldown resistors of the RF

interface.

8. In the “normal” mode the oscillator of the RF chip is controlled via the RFCE pin. Driving the RFCE pin

to logic high level enables the oscillator and the RF chip outputs the BBCLK.

9. Drive the RESET# pin of the LMX5251 high a minimum of 2 ms after the LMX5251 and CP3000

supply rails are powered up. This resets the LMX5251 and CP3SP33.

10. After internal Power-On Reset (POR) of the CP3SP33, the RFDATA pin is driven high. The RFCE,

RFSYNC, and SDAT pins are in TRI-STATE mode. Internal pullup/pulldown resistors on the

CCB_CLOCK (SCLK), CCB_DATA (SDAT), CCB_LATCH (SLE), and TX_RX_SYNC (RFSYNC) inputs

of the LMX5251 pull these signals to states required during the power-up sequence.

11. When the RFDATA pin is driven high, the LMX5251 enables its oscillator. After an oscillator start-up

delay, the LMX5251 drives a stable 12-MHz BBP_CLOCK (CLKIN) to the CP3SP33.

12. The Bluetooth baseband processor on the CP3SP33 now directly controls the RF interface pins and

drives the logic levels required during the power-up phase. When the RFCE pin is driven high, the

LMX5251 switches from “power-up” to “normal” mode and disables the internal pullup/pulldown

resistors on its RF interface inputs.

13. In “normal” mode, the oscillator of the LMX5251 is controlled by the RFCE signal. Driving RFCE high

enables the oscillator, and the LMX5251 drives its BBP_CLOCK (CLKIN) output.

122

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