M38B53M4-059FP datasheet(39/355 Pages) MITSUBISHI

39 / 355 page

38B5 Group User’s Manual

1-23

HARDWARE

FUNCTIONAL DESCRIPTION

Timer 12 mode register

(T12M: address 002816)

Timer 1 count stop bit

0 : Count operation

1 : Count stop

Timer 2 count stop bit

0 : Count operation

1 : Count stop

Timer 1 count source selection bits

00 : f(XIN)/8 or f(XCIN)/16

01 : f(XCIN)

10 : f(XIN)/16 or f(XCIN)/32

11 : f(XIN)/64 or f(XCIN)/128

Timer 2 count source selection bits

00 : Underflow of Timer 1

01 : f(XCIN)

10 : External count input CNTR0

11 : Not available

Timer 1 output selection bit (P45)

0 : I/O port

1 : Timer 1 output

Not used (returns “0” when read)

(Do not write “1” to this bit.)

Timer 34 mode register

(T34M: address 002916)

Timer 3 count stop bit

0 : Count operation

1 : Count stop

Timer 4 count stop bit

0 : Count operation

1 : Count stop

Timer 3 count source selection bits

00 : f(XIN)/8 or f(XCIN)/16

01 : Underflow of Timer 2

10 : f(XIN)/16 or f(XCIN)/32

11 : f(XIN)/64 or f(XCIN)/128

Timer 4 count source selection bits

00 : f(XIN)/8 or f(XCIN)/16

01 : Underflow of Timer 3

10 : External count input CNTR1 (Note)

11 : Not available

Timer 3 output selection bit (P46)

0 : I/O port

1 : Timer 3 output

Not used (returns “0” when read)

(Do not write “1” to this bit.)

Timer 56 mode register

(T56M: address 002A16)

Timer 5 count stop bit

0 : Count operation

1 : Count stop

Timer 6 count stop bit

0 : Count operation

1 : Count stop

Timer 5 count source selection bit

0 : f(XIN)/8 or f(XCIN)/16

1 : Underflow of Timer 4

Timer 6 operation mode selection bit

0 : Timer mode

1 : PWM mode

Timer 6 count source selection bits

00 : f(XIN)/8 or f(XCIN)/16

01 : Underflow of Timer 5

10 : Underflow of Timer 4

11 : Not available

Timer 6 (PWM) output selection bit (P4 4)

0 : I/O port

1 : Timer 6 output

Not used (returns “0” when read)

(Do not write “1” to this bit.)

Note: In the mask option type P, CNTR1 function cannot be used.

Timers

8-Bit Timer

The 38B5 group has six built-in timers : Timer 1, Timer 2, Timer 3,

Timer 4, Timer 5, and Timer 6.

Each timer has the 8-bit timer latch. All timers are down-counters.

When the timer reaches “0016,” an underflow occurs with the next

count pulse. Then the contents of the timer latch is reloaded into the

timer and the timer continues down-counting. When a timer

underflows, the interrupt request bit corresponding to that timer is

set to “1.”

The count can be stopped by setting the stop bit of each timer to “1.”

The internal system clock can be set to either the high-speed mode

or low-speed mode with the CPU mode register. At the same time,

timer internal count source is switched to either f(XIN) or f(XCIN).

qTimer 1, Timer 2

The count sources of timer 1 and timer 2 can be selected by setting

the timer 12 mode register. A rectangular waveform of timer 1 under-

flow signal divided by 2 can be output from the P45/T1OUT pin. The

active edge of the external clock CNTR0 can be switched with the bit

6 of the interrupt edge selection register.

At reset or when executing the STP instruction, all bits of the timer 12

mode register are cleared to “0,” timer 1 is set to “FF16,” and timer 2

is set to “0116.”

qTimer 3, Timer 4

The count sources of timer 3 and timer 4 can be selected by setting

the timer 34 mode register. A rectangular waveform of timer 3 under-

flow signal divided by 2 can be output from the P46/T3OUT pin. The

active edge of the external clock CNTR1 (Note) can be switched with

the bit 7 of the interrupt edge selection register.

Note: In the mask option type P, CNTR1 function cannot be used.

qTimer 5, Timer 6

The count sources of timer 5 and timer 6 can be selected by setting

the timer 56 mode register. A rectangular waveform of timer 6 under-

flow signal divided by 2 can be output from the P44/PWM1 pin.

qTimer 6 PWM1 Mode

Timer 6 can output a PWM rectangular waveform with “H” duty cycle

n/(n+m) from the P44/PWM1 pin by setting the timer 56 mode regis-

ter (refer to Figure 18). The n is the value set in timer 6 latch (address

002516) and m is the value in the timer 6 PWM register (address

002716). If n is “0,” the PWM output is “L,” if m is “0,” the PWM output

is “H” (n = 0 is prior than m = 0). In the PWM mode, interrupts occur

at the rising edge of the PWM output.

Fig. 16 Structure of timer related register

M38B53M4-059FP Datasheet(PDF) 39 Page - Mitsubishi Electric Semiconductor

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