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M38B53M4-059FP Datasheet(PDF) 58 Page - Mitsubishi Electric Semiconductor

Part # M38B53M4-059FP
Description  8-BIT SINGLE-CHIP MICROCOMPUTER
PDF  355 Pages
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Manufacturer  MITSUBISHI [Mitsubishi Electric Semiconductor]
Direct Link  http://www.mitsubishichips.com
Logo MITSUBISHI - Mitsubishi Electric Semiconductor

M38B53M4-059FP Datasheet(HTML) 58 Page - Mitsubishi Electric Semiconductor

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38B5 Group User’s Manual
1-42
HARDWARE
FUNCTIONAL DESCRIPTION
Fig. 43 Segment/Digit setting example
FLD automatic display pins
When the automatic display control bits of the FLDC mode register
(address 0EF416) are set to “1,” the ports of P0, P1, P2, P3 and P8
are used as FLD automatic display pins.
When using the FLD automatic display mode, set each port to the
FLD pin or the general-purpose port using the respective switch reg-
ister in accordance with the number of segments and the number of
digits.
This setting is performed by writing a value into the FLD/port switch
register (addresses 0EF916 to 0EFB16) of each port.
This setting can be performed in units of bit. When “0” is set, the port
is set to the general-purpose port. When “1” is set, the port is set to
the FLD pin. There is no restriction on whether the FLD pin is to be
used as a segment pin or a digit pin.
Table 9 Pins in FLD automatic display mode
Port Name
Automatic Display Pins
Setting Method
P0, P2,
FLD0–FLD15
The individual bits of the FLD/port switch register (addresses 0EF916–0EFB16) can be set each pin
P80–P83
FLD32–FLD35
either FLD port (“1”) or general-purpose port (“0”).
P1, P3
FLD16–FLD31
None (FLD only)
P84–P87
FLD36–FLD39
The individual bits of the FLD/port switch register (address 0EFB16) can be set each pin to either
FLD port (“1”) or general-purpose port (“0”).
The output can be reversed by the port P8 FLD output control register (address 0EFC16).
The port output format is the CMOS output format. When using the port as a display pin, a driver
must be installed externally.
15
8
P24
P25
P26
P27
P20
P21
P22
P23
0
0
0
0
0
0
0
0
FLD16(DIG1)
FLD17(DIG2)
FLD18(DIG3)
FLD19(DIG4)
FLD20(SEG4)
FLD21(SEG5)
FLD22(SEG6)
FLD23(SEG7)
P04
P05
FLD14(SEG2)
FLD15(SEG3)
FLD8(SEG1)
P01
P02
P03
1
0
0
0
0
0
1
1
FLD32(SEG12)
FLD33(SEG13)
FLD34(SEG14)
FLD35(SEG15)
P84
P85
P86
P87
FLD24(SEG8)
FLD25(SEG9)
FLD26(SEG10)
FLD27(SEG11)
FLD28(DIG5)
FLD29(DIG6)
FLD30(DIG7)
FLD31(DIG8)
1
1
1
1
0
0
0
0
25
15
FLD8(SEG9)
FLD9(SEG10)
FLD10(SEG11)
FLD11(SEG12)
FLD12(SEG13)
FLD13(SEG14)
FLD14(SEG15)
FLD15(SEG16)
1
1
1
1
1
1
1
1
FLD0(SEG1)
FLD1(SEG2)
FLD2(SEG3)
FLD3(SEG4)
FLD4(SEG5)
FLD5(SEG6)
FLD6(SEG7)
FLD7(SEG8)
FLD16(DIG1)
FLD17(DIG2)
FLD18(DIG3)
FLD19(DIG4)
FLD20(DIG5)
FLD21(DIG6)
FLD22(DIG7)
FLD23(DIG8)
1
1
1
1
1
1
1
1
FLD24(DIG9)
FLD25(DIG10)
FLD26(DIG11)
FLD27(DIG12)
FLD28(DIG13)
FLD29(DIG14)
FLD30(DIG15)
FLD31(SEG17)
FLD32(SEG18)
FLD33(SEG19)
FLD34(SEG20)
FLD35(SEG21)
1
1
1
1
1
1
1
1
FLD36(SEG22)
FLD37(SEG23)
FLD38(SEG24)
FLD39(SEG25)
18
20
FLD8(DIG1)
FLD9(DIG2)
FLD10(DIG3)
FLD11(DIG4)
FLD12(DIG5)
FLD13(DIG6)
FLD14(DIG7)
FLD15(DIG8)
1
1
1
1
1
1
FLD2(SEG1)
FLD3(SEG2)
FLD4(SEG3)
FLD5(SEG4)
FLD6(SEG5)
FLD7(SEG6)
FLD16(DIG9)
FLD17(DIG10)
FLD18(DIG11)
FLD19(DIG12)
FLD20(DIG13)
FLD21(DIG14)
FLD22(DIG15)
FLD23(DIG16)
1
1
1
1
1
1
1
1
FLD24(DIG17)
FLD25(DIG18)
FLD26(DIG19)
FLD27(DIG20)
FLD28(SEG7)
FLD29(SEG8)
FLD32(SEG11)
FLD33(SEG12)
FLD34(SEG13)
FLD35(SEG14)
1
1
1
1
1
1
1
1
FLD36(SEG15)
FLD37(SEG16)
FLD38(SEG17)
FLD39(SEG18)
16
10
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
P20
P21
P22
P23
FLD4(SEG1)
FLD5(SEG2)
FLD6(SEG3)
FLD7(SEG4)
FLD8(SEG5)
FLD9(SEG6)
FLD10(SEG7)
FLD11(SEG8)
FLD12(SEG9)
FLD13(SEG10)
FLD14(SEG11)
FLD15(SEG12)
FLD16(DIG1)
FLD17(DIG2)
FLD18(DIG3)
FLD19(DIG4)
FLD20(DIG5)
FLD21(DIG6)
FLD22(DIG7)
FLD23(DIG8)
FLD24(DIG9)
FLD25(DIG10)
FLD26(SEG13)
FLD27(SEG14)
FLD28(SEG15)
FLD29(SEG16)
P81
P80
P82
P83
P84
P85
P86
P87
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
P20
P21
FLD30(SEG9)
FLD31(SEG10)
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
P24
P25
Number of segments
Number of digits
Port P2
Setting example 1
Setting example 2
Setting example 3
Setting example 4
Port P0
Port P1
Port P3
Port P8
Value of FLDRAM write disable register
If data is set to “1”, data is protected.
This setting does not decide the FLD
port function (SEG/DIG).
Value of FLD/port switch register



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