M38B53M4-059FP datasheet(13/355 Pages) MITSUBISHI

13 / 355 page

38B5 Group User’s Manual

List of figures

Fig. 2.7.8 Function block diagram ........................................................................................... 2-140

Fig. 2.7.9 Timing chart of data determination ........................................................................ 2-140

Fig. 2.7.10 Setting of relevant registers ................................................................................. 2-141

Fig. 2.7.11 Control procedure ................................................................................................... 2-142

Fig. 2.7.12 Reception of remote-control data (timer 2 interrupt) ........................................ 2-143

Fig. 2.8.1 Memory assignment of watchdog timer relevant register ................................... 2-144

Fig. 2.8.2 Structure of watchdog timer control register ........................................................ 2-144

Fig. 2.8.3 Connection of watchdog timer and setting of division ratio ............................... 2-145

Fig. 2.8.4 Setting of relevant registers ................................................................................... 2-145

Fig. 2.8.5 Control procedure ..................................................................................................... 2-146

Fig. 2.9.1 Memory assignment of buzzer output circuit relevant register .......................... 2-147

Fig. 2.9.2 Structure of buzzer output control register ........................................................... 2-147

Fig. 2.9.3 Connection of buzzer output circuit and setting of division ratio ...................... 2-148

Fig. 2.9.4 Setting of relevant register ..................................................................................... 2-148

Fig. 2.9.5 Control procedure ..................................................................................................... 2-148

Fig. 2.10.1 Example of power-on reset circuit ....................................................................... 2-149

Fig. 2.10.2 RAM backup system example .............................................................................. 2-149

Fig. 2.11.1 Structure of CPU mode register .......................................................................... 2-151

Fig. 2.11.2 Connection diagram ............................................................................................... 2-152

Fig. 2.11.3 Status transition diagram during power failure .................................................. 2-152

Fig. 2.11.4 Setting of relevant registers ................................................................................. 2-153

Fig. 2.11.5 Control procedure ................................................................................................... 2-154

Fig. 2.11.6 Structure of clock counter ..................................................................................... 2-155

Fig. 2.11.7 Initial setting of relevant registers ....................................................................... 2-156

Fig. 2.11.8 Setting of relevant registers after detecting power failure ............................... 2-157

Fig. 2.11.9 Control procedure ................................................................................................... 2-158

CHAPTER 3 APPENDIX

Fig. 3.1.1 Circuit for measuring output switching characteristics ............................................ 3-6

Fig. 3.1.2 Timing diagram ............................................................................................................. 3-7

Fig. 3.2.1 Power source current standard characteristics ........................................................ 3-8

Fig. 3.2.2 Power source current standard characteristics (in wait mode) ............................. 3-8

Fig. 3.2.3 High-breakdown P-channel open-drain output port characteristics (25 °C) ......... 3-9

Fig. 3.2.4 High-breakdown P-channel open-drain output port characteristics (90 °C) ......... 3-9

Fig. 3.2.5 CMOS output port P-channel side characteristics (25 °C) .................................. 3-10

Fig. 3.2.6 CMOS output port P-channel side characteristics (90 °C) .................................. 3-10

Fig. 3.2.7 CMOS output port N-channel side characteristics (25 °C) .................................. 3-11

Fig. 3.2.8 CMOS output port N-channel side characteristics (90 °C) .................................. 3-11

Fig. 3.2.9 N-channel open-drain output port characteristics (25 °C) .................................... 3-12

Fig. 3.2.10 N-channel open-drain output port characteristics (90 °C) .................................. 3-12

Fig. 3.2.11 A-D conversion standard characteristics............................................................... 3-13

Fig. 3.3.1 Sequence of switch detection edge ......................................................................... 3-14

Fig. 3.3.2 Sequence of check of interrupt request bit ............................................................ 3-14

Fig. 3.3.3 Structure of interrupt control register 2 .................................................................. 3-15

Fig. 3.3.4 Sequence of setting serial I/O2 control register again ......................................... 3-18

Fig. 3.3.5 PWM output ................................................................................................................ 3-19

Fig. 3.3.6 Initialization of processor status register ................................................................ 3-22

Fig. 3.3.7 Sequence of PLP instruction execution .................................................................. 3-22

Fig. 3.3.8 Stack memory contents after PHP instruction execution ..................................... 3-22

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