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M38B53M4-059FP Datasheet(PDF) 27 Page - Mitsubishi Electric Semiconductor |
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M38B53M4-059FP Datasheet(HTML) 27 Page - Mitsubishi Electric Semiconductor |
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27 / 355 page  38B5 Group User’s Manual 1-11 HARDWARE FUNCTIONAL DESCRIPTION CPU mode register (CPUM: address 003B16) b7 b0 Stack page selection bit 0: Page 0 1: Page 1 XCOUT drivability selection bit 0: Low drive 1: High drive Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : 1 0 : Not available 1 1 : Port XC switch bit 0: I/O port function 1: XCIN–XCOUT oscillating function Main clock (X IN–XOUT) stop bit 0: Oscillating 1: Stopped Main clock division ratio selection bit 0: f(XIN) (high-speed mode) 1: f(XIN)/4 (middle-speed mode) Internal system clock selection bit 0: XIN-XOUT selection (middle-/high-speed mode) 1: XCIN-XCOUT selection (low-speed mode) [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit and the internal system clock selection bit etc. The CPU mode register is allocated at address 003B16. Fig. 7 Structure of CPU mode register |
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