M38B53M4-059FP datasheet(57/355 Pages) MITSUBISHI

57 / 355 page

38B5 Group User’s Manual

1-41

HARDWARE

FUNCTIONAL DESCRIPTION

[FLDC Mode Register] FLDM

The FLDC mode register is a 8-bit register respectively which is used

to control the FLD automatic display and to set the blanking time

Tscan for key-scan.

Fig. 42 Structure of FLDC mode register

FLDC mode register

(FLDM: address 0EF416)

Automatic display control bit (P0, P1, P2, P3, P8)

0 : General-purpose mode

1 : Automatic display mode

Display start bit

0 : Stop display

1 : Display

(start to display by switching “0” to “1”)

Tscan control bits

00 : FLD digit interrupt (at rising edge of each digit)

01 : 1 ! Tdisp

10 : 2 ! Tdisp

11 : 3 ! Tdisp

Timing number control bit

0 : 16 timing mode

1 : 32 timing mode

Gradation display mode selection control bit

0 : Not selecting

1 : Selecting (Note)

Tdisp counter count source selection bit

0 : f(XIN)/16 or f(XCIN)/32

1 : f(XIN)/64 or f(XCIN)/128

High-breakdown voltage port drivability selection bit

0 : Drivability strong

1 : Drivability weak

FLD blanking interrupt

(at falling edge of the last digit)

Notes 1: When a gradation display mode is selected, a number of timing is max. 16

timing. (Set the timing number control bit to “0.”)

2: When changing bit 4 (timing number control bit) or bit 5 (gradation display

mode selection control bit), set “0” to bit 1 (display start bit) to perform at

display stop state.

M38B53M4-059FP Datasheet(PDF) 57 Page - Mitsubishi Electric Semiconductor

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