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M38B53M4-059FP Datasheet(PDF) 106 Page - Mitsubishi Electric Semiconductor |
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M38B53M4-059FP Datasheet(HTML) 106 Page - Mitsubishi Electric Semiconductor |
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106 / 355 page  2-18 38B5 Group User’s Manual APPLICATION 2.2 Timer Fig. 2.2.14 Structure of Interrupt control register 2 Interrupt control register 2 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 2 (ICON2 : address 3F16) b 0 0 1 2 3 4 Name 0 Functions At reset R W 0 0 0 0 Timer 5 interrupt enable bit Serial I/O2 receive interrupt enable bit INT3/Serial I/O2 transmit interrupt enable bit (Note) Timer 6 interrupt enable bit 0 : interrupt disabled 1 : Interrupt enabled 0 : interrupt disabled 1 : Interrupt enabled 0 : interrupt disabled 1 : Interrupt enabled 0 : interrupt disabled 1 : Interrupt enabled 0 : interrupt disabled 1 : Interrupt enabled 5 0 INT4 interrupt enable bit A-D converter interrupt enable bit 0 : interrupt disabled 1 : Interrupt enabled 6 7 0 FLD blanking interrupt enable bit FLD digit interrupt enable bit 0 : interrupt disabled 1 : Interrupt enabled 0 Fix “0” to this bit. Timer 4 interrupt enable bit (Note) Note: In the mask option type P, timer 4 interrupt whose count source is CNTR1 input and INT3 interrupt are not available. 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled Interrupt control register 1 b7 b6 b5 b4 b3 b2 b1 b0 Interrupt control register 1 (ICON1 : address 3E16) b 0 1 2 3 4 5 6 7 Name 0 Functions At reset R W 0 0 0 0 INT0 interrupt enable bit INT1 interrupt enable bit Serial I/O1 interrupt enable bit Serial I/O automatic transfer interrupt enable bit Timer X interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit INT2 interrupt enable bit Remote controller /counter overflow interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled Timer 3 interrupt enable bit 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 : Interrupt disabled 1 : Interrupt enabled 0 0 0 Fig. 2.2.13 Structure of Interrupt control register 1 |
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