M38B53M4-059FP datasheet(179/355 Pages) MITSUBISHI

179 / 355 page

2-91

38B5 Group User’s Manual

APPLICATION

2.4 FLD controller

Fig. 2.4.12 Structure of port P8FLD output control register

Fig. 2.4.13 Structure of interrupt request register 2

R W

Port P8FLD output control register

b7 b6 b5 b4 b3 b2 b1 b0

Port P8FLD output control register

(P8FLDCON : address 0EFC16)

Name

Functions

At reset

P84–P87 FLD

output reverse bit

P84–P87/FLDRAM

write disable bit

0 : Output normally

1 : Reverse output

0 : Operating normally

1 : Write disabled

P84–P87 Toff

invalid bit

0 : Operating normally

1 : Toff invalid

P84–P87 delay

control bit (Note)

0 : No delay

1 : Delay

P63/AN9 dimmer

output control bit

0 : Ordinary port

1 : Dimmer output

Nothing is arranged for these bits. These are

write disabled bits. When these bits are read

out, the contents are “0”.

Toff2 control bit

0 : Operating normally

(falling operation)

1 : Rising operation

Note: Valid only when selecting FLD port and P84–P87 Toff invalid function

Interrupt request register 2

b7 b6 b5 b4 b3 b2 b1 b0

Interrupt request register 2

(IREQ2 : address 3D16)

Name

Functions

At reset R W

Timer 4 interrupt

request bit (Note)

Timer 5 interrupt

request bit

Serial I/O2 receive

interrupt request bit

INT3/serial I/O2

transmit interrupt

request bit (Note)

INT4 interrupt

request bit

A-D converter

interrupt request bit

FLD blanking

interrupt request bit

FLD digit interrupt

request bit

Timer 6 interrupt

request bit

Nothing is arranged for this bit. This is a write

disabled bit. When this bit is read out, the contents

are “0”.

V: “0” can be set by software, but “1” cannot be set.

Note: In the mask option type P, if timer 4 interrupt whose count source is

CNTR1 input and INT3 interrupt are selected, these bits do not

become “1”.