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M38B53M4-059FP Datasheet(PDF) 246 Page - Mitsubishi Electric Semiconductor |
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M38B53M4-059FP Datasheet(HTML) 246 Page - Mitsubishi Electric Semiconductor |
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246 / 355 page  2-158 38B5 Group User’s Manual APPLICATION 2.11 Clock generating circuit Control procedure: Set the relevant registers in the order shown below to prepare for a power failure. Fig. 2.11.9 Control procedure Initialization T12M (address 002816), bit 3, bit 2 ICON1 (address 003E16), bit 5 CPUM (address 003B16), bit 7 CPUM (address 003B16), bit 5 IREQ1 (address 003C16), bit 7, bit 5 T1 (address 002016) T2 (address 002116) T3 (address 002216) 0, 1 0 1 (Note) 1 (Note) 0, 0 0716 3F16 0F16 RESET Timer 1 count source: f(XCIN) Timer 1 interrupt: Disabled Internal system clock: f(XCIN) (low-speed mode) Main clock f(XIN): Oscillation stopped Setting for generating timer 3 interrupt every second Generation of one second by hardware timer during power failure Note: Do not switch at one time. Return processing from power failure Execute WIT instruction Timer 3 interrupt occurs every second (return from wait mode) Port XC: XCIN-XCOUT oscillation function When selecting main clock f(XIN) (high-speed mode) Setting for making base and one second counters activate during timer 1 interrupt In the normal power state, these software counters generate one second. Detect power failure ? N Y Return condition for power failure is satisfied ? N Y ICON1 (address 003E16), bit 7 1 Timer 3 interrupt: Enabled qX: This bit is not used here. Set it to “0” or “1” arbitrarily. 1 0 3F16 000010002 00XX01X02 0,0 FF16 0F16 1 CPUM (address 003B16), bit 4 CPUM (address 003B16), bit 6 T1 (address 002016) T12M (address 002816) T34M (address 002916) IREQ1 (address 003C16), bit 7, bit 5 Base counter (internal RAM) 1 second counter (internal RAM) ICON1 (address 003E16), bit 5 ≈ ≈ |
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