M38B53M4-059FP datasheet(284/355 Pages) MITSUBISHI

284 / 355 page

3-36

APPENDIX

38B5 Group User’s Manual

3.5 Control registers

Fig. 3.5.8 Structure of PWM register (low-order)

Fig. 3.5.7 Structure of PWM register (high-order)

Functions

At reset R W

Undefined

PWM register (high-order)

b7 b6 b5 b4 b3 b2 b1 b0

PWM register (high-order)

(PWMH: address 1416)

• High-order 8 bits of PWM0 output data is set.

• The values set in this register is transferred to

the PWM latch each sub-period cycle (64

µs).

(At f(XIN) = 4 MHz)

• When this register is read out, the value of the

PWM register (high-order) is read out.

Functions

At reset R W

Undefined

PWM register (low-order)

b7 b6 b5 b4 b3 b2 b1 b0

PWM register (low-order)

(PWML: address 1516)

• Low-order 6 bits of PWM0 output data is set.

• The values set in this register is transferred to

the PWM latch at each PWM cycle period

(4096

µs).

(At f(XIN) = 4 MHz)

• When this register is read out, the value of the

PWM latch (low-order 6 bits) is read out.

Nothing is arranged for this bit. This bit is a

write disabled bit. When this bit is read out, the

contents are “0”.

• This bit indicates whether the transfer to the

PWM latch is completed.

0: Transfer is completed

1: Transfer is not completed

• This bit is set to “1” at writing.

M38B53M4-059FP Datasheet(PDF) 284 Page - Mitsubishi Electric Semiconductor

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