M38B53M4-059FP datasheet(314/355 Pages) MITSUBISHI

314 / 355 page

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APPENDIX

38B5 Group User’s Manual

3.5 Control registers

Fig. 3.5.54 Structure of port P8FLD output control register

Fig. 3.5.55 Structure of buzzer output control register

R W

Port P8FLD output control register

b7 b6 b5 b4 b3 b2 b1 b0

Port P8FLD output control register

(P8FLDCON : address 0EFC16)

Name

Functions

At reset

P84–P87 FLD

output reverse bit

P84–P87/FLDRAM

write disable bit

0 : Output normally

1 : Reverse output

0 : Operating normally

1 : Write disabled

P84–P87 Toff

invalid bit

0 : Operating normally

1 : Toff invalid

P84–P87 delay

control bit (Note)

0 : No delay

1 : Delay

P63/AN9 dimmer

output control bit

0 : Ordinary port

1 : Dimmer output

Nothing is arranged for these bits. These are

write disabled bits. When these bits are read

out, the contents are “0”.

Toff2 control bit

0 : Operating normally

(falling operation)

1 : Rising operation

Note: Valid only when selecting FLD port and P84–P87 Toff invalid function

Buzzer output control register

b7 b6 b5 b4 b3 b2 b1 b0

Buzzer output control register

(BUZCON: address 0EFD16)

Name

Functions

At reset R W

0: Buzzer output OFF (“0”

output)

1: Buzzer output ON

b1b0

0 0: 1 kHz (f(XIN)/4096)

0 1: 2 kHz (f(XIN)/2048)

1 0: 4 kHz (f(XIN)/1024)

1 1: Not available

Output frequency

selection bits

b3b2

0 0: P20 and P43 function

as ordinary ports.

0 1: P43/BUZ01 functions as

a buzzer output.

1 0: P20/BUZ02/FLD0

functions as a buzzer

output.

1 1: Not available

Output port

selection bits

Buzzer output

ON/OFF bit

Nothing is arranged for these bits. These are

write disabled bits. When these bits are read

out, the contents are “0”.

M38B53M4-059FP Datasheet(PDF) 314 Page - Mitsubishi Electric Semiconductor

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