SST49LF016C datasheet(14/43 Pages) MICROCHIP

14 / 43 page

DS20005029B

02/16

16 Mbit LPC Serial Flash

SST49LF016C

EOL Data Sheet

Abort Mechanism

If LFRAME# is driven low for one or more clock cycles after the start of a bus cycle, the cycle will be

terminated. The host may drive the LAD[3:0] with ‘1111b’ (ABORT nibble) to return the interface to

ready mode. The ABORT only affects the current bus cycle. For a multi-cycle command sequence,

such as the Erase or Program commands, ABORT doesn’t interrupt the entire command sequence,

only the current bus cycle of the command sequence. The host can re-send the bus cycle for the

aborted command and continue the command sequence after the device is ready again.

Response to Invalid Fields for Firmware Memory Cycle

During an on-going Firmware Memory bus cycle, the SST49LF016C will not explicitly indicate that it

has received invalid field sequences. The response to specific invalid fields or sequences is described

as follows:

ID mismatch:

If the IDSEL field does not match ID[3:0], the device will ignore the cycle. See “Multiple Device Selec-

tion for Firmware Memory Cycle” on page 15 for details.

Address out of range:

The address sequence is 7 fields long (28 bits) with Firmware Memory bus cycles. Only some of the

address fields bits are decoded by the SST49LF016C. These are: A0 through A20 and A22. Address

A22 has the special function of directing reads and writes to the flash core (A22=1) or to the register

space (A22=0).

Invalid MSIZE field:

If the SST49LF016C receives an invalid size field during a Firmware Memory Read or Write operation,

the device will reset and no operation will be attempted. The device will not generate any kind of

response in this situation. The SST49LF016C will only respond to values listed in Table 6.

Once valid START, IDSEL, and MSIZE are received, the SST49LF016C will always complete the bus

cycle. However, if the device is busy performing a flash Erase or Program operation, no new internal

memory Write will be executed. As long as the states of LAD[3:0] and LFRAME# are known, the

response of the ST49LF016C to signals received during the cycle is predictable.

Table 6: Valid MSIZE field Values for Firmware Memory Cycles

MSIZE

Direction

Size of Transfer

0000

R/W

1 Byte

0001

R/W

2 Byte

0010

R/W

4 Byte

0100

16 Byte

0111

128 Byte

T6.0 20005029

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