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TMS320DM814X Datasheet(PDF) 183 Page - Texas Instruments |
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TMS320DM814X Datasheet(HTML) 183 Page - Texas Instruments |
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183 / 377 page  TMS320DM8148, TMS320DM8147 www.ti.com SPRS647E – MARCH 2011 – REVISED DECEMBER 2013 7.2.2.1 Dynamic Voltage Frequency Scaling (DVFS) Each device Core Logic Voltage Domain can be run independently at one of several Operating Performance Points (OPPs). An OPP for a specific Core Logic Voltage Domain is defined by: (1) maximum frequencies of operation for Modules within the Domain and (2) an associated supply voltage range. Trading off power versus performance, OPPs with lower maximum frequencies also have lower voltage ranges for power savings. The OPP for a domain can be changed in real-time without requiring a reset. This feature is called Dynamic Voltage Frequency Scaling (DVFS). Table 7-4 contains a list of voltage ranges and maximum module frequencies for the OPPs of each Core Logic Voltage Domain. Table 7-4. Device Operating Points (OPPs) CORE LOGIC VOLTAGE DOMAINS ARM DSP HDVICP CORE L3/L4, Cortex A8 DSP HDVICP2 HDVPSS SGX ISS Media Ctlr. DDR OPP Core (MHz) (MHz) (MHz) (MHz) (MHz) (MHz) (MHz) (MHz)(1) (MHz) 100% 600 500 266 200 200 400 200 200 400 (1.1 V) 120% 720 600 306 200 250 400 200 220 400 (1.2 V) 166% 700 (CYE1) 1000 410 220 280 480 240 220 533 750(2) (1.35 V) 166% (CYE2) 1000 750 450 220 280 560 280 220 533 (1.35 V) (1) All DDR access must be suspended prior to changing the DDR frequency of operation. (2) Only DM814x SR3.0 devices support a DSP Frequency of 750-MHz. For more details on device silicon revisions, see Figure 9-1, Device Nomenclature. Although the OPP for each Core Logic Voltage Domain is independently selectable, not all combinations of OPPs are supported. Table 7-5 marks the supported ARM, DSP, and HDVICP2 OPPs for a given CORE OPP. Table 7-5. Supported OPP Combinations(1)(2) ARM DSP HDVICP2 CORE OPP166 OPP120 OPP100 OPP166 OPP120 OPP100 OPP166 OPP120 OPP100 OPP166 X X X OPP120 X X X X X X OPP100 X X X X X X (1) "X" denotes supported combinations. (2) The maximum voltage differences between CVDD and any other CVDD_x voltage domain must be < 150 mV. 7.2.2.2 Adaptive Voltage Scaling [Not Supported] As mentioned in Section 7.2.2.1, Dynamic Voltage Frequency Scaling (DVFS) above, every OPP has an associated voltage range. Based on the silicon process, temperature, and chosen OPP, the SmartReflex modules guide software in adjusting the Core Logic Voltage Domain supply voltages within these ranges. This technique is called Adaptive Voltage Scaling (AVS). AVS occurs continuously and in real-time, helping to minimize power consumption in response to changing operating conditions. 7.2.3 Memory Power Management To reduce SRAM leakage, many SRAM blocks can be switched from ACTIVE mode to SHUTDOWN mode. When SRAM is put in SHUTDOWN mode, the voltage supplied to it is automatically removed and all data in that SRAM is lost. Copyright © 2011–2013, Texas Instruments Incorporated Power, Reset, Clocking, and Interrupts 183 Submit Documentation Feedback Product Folder Links: TMS320DM8148 TMS320DM8147 |
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