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TMS320DM814X Datasheet(PDF) 210 Page - Texas Instruments |
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TMS320DM814X Datasheet(HTML) 210 Page - Texas Instruments |
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210 / 377 page ![]() TMS320DM8148, TMS320DM8147 SPRS647E – MARCH 2011 – REVISED DECEMBER 2013 www.ti.com Table 7-23. Top-Level PLL Frequency Ranges (ALL OPPs) (continued) CLOCK MIN MAX UNIT CLKOUT see Table 7-25 see Table 7-25 MHz Table 7-24. ARM Cortex-A8 Embedded PLL (PLL_ARM) Frequency Ranges (ALL OPPs) CLOCK MIN MAX UNIT REFCLK 0.032 52 MHz DCOCLK 20 2000 MHz CLKOUT see Table 7-25 see Table 7-25 MHz Table 7-25. PLL CLKOUT Frequency Ranges OPP100 PLL UNIT MIN MAX PLL_ARM 10 600 MHz PLL_DSP 10 500 MHz PLL_SGX 10 200 MHz PLL_HDVICP 10 266 MHz PLL_L3 10 200 MHz PLL_DDR 10 400 MHz PLL_HDVPSS 10 200 MHz PLL_AUDIO 10 200 MHz PLL_MEDIACTL 10 400 MHz PLL_USB 10(1) 960 MHz PLL_VIDEO0 10 200 MHz PLL_VIDEO1 10 200 MHz PLL_VIDEO2 10 200 MHz (1) When the USB is used, PLL_USB must be fixed at 960 MHz. 7.4.8.4 PLL Register Descriptions The PLL Control Registers reside in the Control Module and are listed in Section 4.1, Control Module of this datasheet. 210 Power, Reset, Clocking, and Interrupts Copyright © 2011–2013, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Links: TMS320DM8148 TMS320DM8147 |
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