TMS320DM814X datasheet(209/377 Pages) TI1

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TMS320DM8148, TMS320DM8147

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SPRS647E – MARCH 2011 – REVISED DECEMBER 2013

7.4.8.1

PLL Power Supply Filtering

The device PLLs are supplied externally via the VDDA_xPLL_1P8 power-supply pins (where "x"

represents ARM, DSP, VID0, VID1, AUDIO, DDR, and/or L3). External filtering must be added on the PLL

supply pins to ensure that the requirements in Table 7-20 are met.

Table 7-20. PLL Power Supply Requirements

PARAMETER

MIN

MAX

UNIT

Dynamic noise at VDDA_xPLL_1P8 pins

mV p-p

7.4.8.2

PLL Multipliers and Dividers

The Top-Level and PLL_ARM PLLs support the internal multiplier and divider values shown in Table 7-21,

Top-Level PLL Multiplier and Divider Limits and Table 7-22, PLL_ARM Multiplier and Divider Limits. The

PLLs must be programmed to conform to the various REFCLK, CLKDCO, DCOCLK, and CLKOUT limits

described in Section 7.4.8.3, PLL Frequency Limits.

Table 7-21. Top-Level PLL Multiplier and Divider Limits

PARAMETER

MIN

MAX

N Pre-Divider

255

PLL Multiplier (M)

4095(1)

M2 Post Divider

127

N2 Bypass Divider

(1)

The PLL Multiplier supports fractional values (up to 18-bits of fraction) except when the PLL Multiplier is > 4093.

Table 7-22. PLL_ARM Multiplier and Divider Limits

PARAMETER

MIN

MAX

N Pre-Divider

127

PLL Multiplier (M)(1)

2047(2)

M2 Post Divider

N2 Bypass Divider

(1)

This parameter describes the limits on the programmable multiplier value M. The multiplication factor for the PLL_ARM is equal to 2 * M

(also see Figure 7-18).

(2)

The PLL Multiplier supports fractional values (up to 18-bits of fraction) except when the PLL Multiplier is < 20 OR > 2045.

7.4.8.3

PLL Frequency Limits

Each PLL supports a minimum and maximum operating frequency for its REFCLK, CKLDCO, and

CLKOUT values. The PLLs must be configured not to exceed any of the constraints placed on these

values shown in Table 7-23 through Table 7-25. Care must be taken to stay within these limits when

selecting external clock input frequencies, internal divider values, and PLL multiply ratios. In addition,

limits shown in these tables may be further restricted by the clock frequency limitations of the device

modules using these clocks. For more detailed information on the SYSCLK and Module Clock frequency

limits, see Section 7.4.9, SYSCLKs and Section 7.4.10, Module Clocks.

Table 7-23. Top-Level PLL Frequency Ranges (ALL OPPs)

CLOCK

MIN

MAX

UNIT

REFCLK

0.5

2.5

MHz

CLKDCO (HS1)(1)

1000

2000

MHz

CLKDCO (HS2)(2)

500

1000

MHz

(1)

The PLL has two modes of operation: HS1 and HS2. The mode of operation should be set, according to the desired CLKDCO

frequency, by programming the SELFREQDCO field of the ADPLLLJx_CLKCTRL registers in the Control Module.

(2)

CLKDCO of the PLL_USB is used undivided by the USB modules; therefore, CLKDCO for the PLL_USB PLL must be programmed to

960 MHz for proper operation.

Power, Reset, Clocking, and Interrupts

209

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