TMS320DM814X datasheet(303/377 Pages) TI1

303 / 377 page

TMS320DM8148, TMS320DM8147

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SPRS647E – MARCH 2011 – REVISED DECEMBER 2013

8.13.4.2.4 DDR3 Interface Schematic

The DDR3 interface schematic varies, depending upon the width of the DDR3 devices used and the width

of the bus used (16 or 32 bits). General connectivity is straightforward and very similar. 16-bit DDR

devices look like two 8-bit devices. Figure 8-54 and Figure 8-55 show the schematic connections for 32-bit

interfaces using x16 and x8 devices.

Note that a 16-bit wide interface schematic is practically identical to the 32-bit interface; only the high-word

DDR memories are removed.

When not using all or part of a DDR3 interface, the proper method of handling the unused pins is to tie off

the DDR[x]_DQS[n] pins to the corresponding DVDD_DDR[x] supply via a 1-k

Ω resistor and pulling the

DDR[x]_DQS[n] pins to ground via a 1k-

Ω resistor. This needs to be done for each byte not used.

Although these signals have internal pullups and pulldowns, external pullups and pulldowns provide

additional protection against external electrical noise causing activity on the signals.Also, include the 50-

pulldown for DDR[x]_VTP. The DVDD_DDR[x] and VREFSSTL_DDR[x] power supply pins need to be

connected to their respective power supplies even if DDR[x] is not being used. All other DDR interface

pins can be left unconnected. Note that the supported modes for use of the DDR EMIF are 32 bits wide,

16 bits wide, or not used.

Peripheral Information and Timings

303

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TMS320DM814X Datasheet(PDF) 303 Page - Texas Instruments