TMS320DM814X datasheet(307/377 Pages) TI1

307 / 377 page

DDR3

Controller

TMS320DM8148, TMS320DM8147

www.ti.com

SPRS647E – MARCH 2011 – REVISED DECEMBER 2013

Table 8-69. PCB Stackup Specifications

NO.

PARAMETER

MIN

TYP

MAX

UNIT

PCB routing/plane layers

Signal routing layers

Full ground reference layers under DDR3 routing region(1)

Full 1.5-V power reference layers under the DDR3 routing region(1)

Number of reference plane cuts allowed within DDR routing region(2)

Number of layers between DDR3 routing layer and reference plane(3)

PCB routing feature size

Mils

PCB trace width, w

Mils

Single-ended impedance, Zo

Ω

Impedance control(4)

Z-5

Z+5

Ω

(1)

Ground reference layers are preferred over power reference layers. Be sure to include bypass caps to accommodate reference layer

return current as the trace routes switch routing layers.

(2)

No traces should cross reference plane cuts within the DDR routing region. High-speed signal traces crossing reference plane cuts

create large return current paths which can lead to excessive crosstalk and EMI radiation.

(3)

Reference planes are to be directly adjacent to the signal plane to minimize the size of the return current loop.

(4)

Z is the nominal singled-ended impedance selected for the PCB specified by item 13.

8.13.4.2.4.3 Placement

Figure 8-56 shows the required placement for the processor as well as the DDR3 devices. The

dimensions for this figure are defined in Table 8-70. The placement does not restrict the side of the PCB

on which the devices are mounted. The ultimate purpose of the placement is to limit the maximum trace

lengths and allow for proper routing space. For a 16-bit DDR memory system, the high-word DDR3

device(s) are omitted from the placement.

Figure 8-56. Placement Specifications

It is strongly recommended that high-speed bypass capacitors be placed and accommodated for during

the placement and route planning phase. It is very difficult to add bypass capacitors once the board has

been routed and significant rework may be required to meet the high-speed bypass capacitor

requirements in Section 8.13.4.2.4.6, High-Speed Bypass Capacitors if the proper planning is not done. A

particular challenge to placing bypass capacitors in congested areas is fitting the required vias. It is

suggested that each pair of vias support two bypass capacitors by mounting one capacitor on the top of

the board and other on the bottom. Do not share vias between capacitors mounted on the same side of

the PCB. Another suggestion is to line up the vias for the bypass capacitors for the processor in rows

forming channels to allow the signals to escape.

Peripheral Information and Timings

307

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