TMS320DM814X datasheet(308/377 Pages) TI1

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DDR[0] Keep Out Region

Encompasses Entire DDR[0] Routing Area

DDR3 Controllers

DDR[1] Keep Out Region

Encompasses Entire DDR[1] Routing Area

TMS320DM8148, TMS320DM8147

SPRS647E – MARCH 2011 – REVISED DECEMBER 2013

www.ti.com

Table 8-70. Placement Specifications

NO.

PARAMETER

MIN

MAX

UNIT

X1(1)(2)(3)

1000

Mils

X2(1)(2)

600

Mils

Y Offset(1)(2)(3)

1500

Mils

DDR3 keepout region

Clearance from non-DDR3 signal to DDR3 keepout region(4)(5)(6)

(1)

For dimension definitions, see Figure 8-56.

(2)

Measurements from center of processor to center of DDR3 device.

(3)

Minimizing X1 and Y improves timing margins.

(4)

w is defined as the signal trace width.

(5)

Non-DDR3 signals allowed within DDR3 keepout region provided they are separated from DDR3 routing layers by a ground plane.

(6)

If a device has more than one DDR controller, the signals from the other controller(s) are considered non-DDR3 and should be

separated by this specification.

8.13.4.2.4.4 DDR3 Keepout Region

The region of the PCB used for DDR3 circuitry must be isolated from other signals. The DDR3 keepout

region is defined for this purpose and is shown in Figure 8-57. The size of this region varies with the

placement and DDR routing. Additional clearances required for the keepout region are shown in Table 8-

70. Non-DDR3 signals should not be routed on the DDR signal layers within the DDR3 keepout region.

Non-DDR3 signals may be routed in the region, provided they are routed on layers separated from the

DDR signal layers by a ground layer. No breaks should be allowed in the reference ground layers in this

region. In addition, the 1.5-V DDR3 power plane should cover the entire keepout region. Also note that if

there is more than one DDR controller, the signals from each controller need to be separated from each

other by the specification in Table 8-70, item 5. Each DDR controller should have its own DDR keepout

region.

Figure 8-57. DDR3 Keepout Region

Figure 8-57 is an example of a processor with two DDR controllers. Processors with a single DDR

controler will have only one DDR keepout region. Each DDR controller should have its own keepout

region.

8.13.4.2.4.5 Bulk Bypass Capacitors

Bulk bypass capacitors are required for moderate speed bypassing of the DDR3 and other circuitry.

Table 8-71 contains the minimum numbers and capacitance required for the bulk bypass capacitors. Note

that this table only covers the bypass needs of the DDR3 controllers and DDR3 device(s). Additional bulk

bypass capacitance may be needed for other circuitry.

308

Peripheral Information and Timings

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