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TMS320DM814X Datasheet(PDF) 355 Page - Texas Instruments

Part # TMS320DM814X
Description  DaVinci Video Processors
PDF  377 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

TMS320DM814X Datasheet(HTML) 355 Page - Texas Instruments

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SPI_SCS[x] (Out)
SPI_SCLK (Out)
SPI_SCLK (Out)
SPI_D[x] (In)
Bit n-1
Bit n-2
Bit n-3
Bit n-4
Bit 0
PHA=0
EPOL=1
POL=0
POL=1
8
9
3
4
2
1
2
3
5
SPI_SCS[x] (Out)
SPI_SCLK (Out)
SPI_SCLK (Out)
SPI_D[x] (In)
Bit n-1
Bit n-2
Bit n-3
Bit 1
Bit 0
PHA=1
EPOL=1
POL=0
POL=1
8
9
3
2
1
2
3
1
4
5
4
5
5
4
1
TMS320DM8148, TMS320DM8147
www.ti.com
SPRS647E – MARCH 2011 – REVISED DECEMBER 2013
Figure 8-91. SPI Master Mode Receive Timing
Table 8-106. Timing Requirements for SPI - Slave Mode
(see Figure 8-92 and Figure 8-93)
OPP100/120/166
NO.
UNIT
MIN
MAX
1
tc(SPICLK)
Cycle time, SPI_CLK(1)(2)
62.5(3)
ns
2
tw(SPICLKL)
Pulse duration, SPI_CLK low(1)
0.5*P - 3(4)
ns
3
tw(SPICLKH)
Pulse duration, SPI_CLK high(1)
0.5*P - 3(4)
ns
4
tsu(MOSI-SPICLK)
Setup time, SPI_D[x] valid before SPI_CLK active edge (1)
12.92
ns
5
th(SPICLK-MOSI)
Hold time, SPI_D[x] valid after SPI_CLK active edge (1)
12.92
ns
6
td(SPICLK-MISO)
Delay time, SPI_CLK active edge to SPI_D[x] transition (1)
-4.00
17.1
ns
Delay time, SPI_SCS[x] active edge to SPI_D[x]
7
td(SCS-MISO)
17.1
ns
transition(5)
8
tsu(SCS-SPICLK)
Setup time, SPI_SCS[x] valid before SPI_CLK first edge (1)
12.92
ns
(1)
This timing applies to all configurations regardless of SPI_CLK polarity and which clock edges are used to drive output data and capture
input data.
(2)
Related to the input maximum frequency supported by the SPI module.
(3)
Maximum frequency = 16 MHz
(4)
P = SPICLK period.
(5)
PHA = 0; SPI_CLK phase is programmable with the PHA bit of the SPI_CH(i)CONF register.
Copyright © 2011–2013, Texas Instruments Incorporated
Peripheral Information and Timings
355
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Product Folder Links: TMS320DM8148 TMS320DM8147



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