115F40-R000RA-M3 datasheet(13/39 Pages) AUO

13 / 39 page

Product Specification

M270DTN01.5

CN3

PIN #

Symbol

DESCRIPTION

R5_0N

Negative LVDS differential data input (Port5 data)

R5_0P

Positive LVDS differential data input (Port5 data)

R5 1N

Negative LVDS differential data input (Port5 data)

R5 1P

Positive LVDS differential data input (Port5 data)

R5 2N

Negative LVDS differential data input (Port5 data)

R5 2P

Positive LVDS differential data input (Port5 data)

GND

Ground

R5_CLKN

Negative LVDS differential clock input (Port5 clock)

R5_CLKP

Positive LVDS differential clock input (Port5 clock)

GND

Ground

R5 3N

Negative LVDS differential data input (Port5 data)

R5 3P

Positive LVDS differential data input (Port5 data)

No connection (for AUO test only. Do not connect)

GND

Ground

R6_0N

Negative LVDS differential data input (Port6 data)

R6_0P

Positive LVDS differential data input (Port6 data)

R6_1N

Negative LVDS differential data input (Port6 data)

R6_1P

Positive LVDS differential data input (Port6 data)

R6 2N

Negative LVDS differential data input (Port6 data)

R6 2P

Positive LVDS differential data input (Port6 data)

GND

Ground

R6 CLKP

Negative LVDS differential clock input (Port6 clock)

R6 CLKP

Positive LVDS differential clock input (Port6 clock)

GND

Ground

R6_3N

Negative LVDS differential data input (Port6 data)

R6_3P

Positive LVDS differential data input (Port6 data)

No connection (for AUO test only. Do not connect)

3D_EN (I)

115F40-R000RA-M3 Datasheet(PDF) 13 Page - AU Optronics Corp.,

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