NM1482KSLAXCL datasheet(36/121 Pages) NANYA

36 / 121 page

Version 1.6

Nanya Technology Corp.

05/2018

4Gb SLC NAND + 2Gb LPDDR2

NM148(F)2KSLAXCL/NM1482NSLAXCL

NTC Proprietary

Level: Property

Starting the above operation from 1st page of the selected erase blocks, and then repeating the operation

total 64 times with incrementing the page address in the blocks, and then input the last page data of the

blocks, “10h” command executes final programming. Make sure to terminate with 81h-10h- command

sequence.

In this full sequence, the command sequence is following.

After the “15h” or “10h” command, the results of the above operation is shown through the “71h”Status Read

command.

The 71H Command Status Description

I/O

Status

Output

I/O 0

Chip Status1 : Pass / Fail

Pass : 0 / Fail : 1

I/O 1

District 0 Chip Status1 : Pass / Fail

Pass : 0 / Fail : 1

I/O 2

District 1 Chip Status2 : Pass / Fail

Pass : 0 / Fail : 1

I/O 3

District 0 Chip Status1 : Pass / Fail

Pass : 0 / Fail : 1

I/O 4

District 1 Chip Status2 : Pass / Fail

Pass : 0 / Fail : 1

I/O 5

Ready / Busy

Busy : 0 / Ready : 1

I/O 6

Data Cache Ready / Busy

Busy : 0 / Ready : 1

I/O 7

Write Protect

Protected : 0 / Not Protected : 1

I/O0 describes Pass/Fail condition of district 0 and 1 (OR data of I/O1 and I/O2). If one of the districts fails during multi

page program operation, it shows “Fail”.

I/O1 to I/O4 shows the Pass/Fail condition of each district. For details on “Chip Status 1” and “Chip Status2” refer to

section “Status Read”.

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