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STA450A Datasheet(PDF) 61 Page - STMicroelectronics |
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STA450A Datasheet(HTML) 61 Page - STMicroelectronics |
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61 / 66 page  61/66 STA450A a) OCLK in output. The audio PLL is used to clock the DAC Notations: Cload_XXX is the load in pF on the XXX output. pad_timing(Cload_XXX) is the propagation delay added to the XXX pad due to the load. The following table gives this timing . tsdo_max = 3.5 + pad_timing(Cload_SDO) - pad_timing(Cload_OCLK) tsckt_max = 4.0 + pad_timing(Cload_SCKT) - pad_timing(Cload_OCLK) tlrckt_max = 3.5 + pad_timing(Cload_LRCKT) - pad_timing(Cload_OCLK) The Tr and Tf depends on the load on the different pads but at a given load, the Tr and Tf timings are identical for OCLK(output case), SCKT, LRCKT, SDO. b) OCLK in input Thi min = 5 ns Tlo min = 5 ns Toclk min = 25 ns tsdo_max = 5.5 + pad_timing(Cload_SDO) ns Load (pF) max pad_timing (rise) max pad_timing (fall) 25 6 ns 10.6 ns 50 10 ns 13 ns 75 12 ns 15.4 ns 100 14 ns 18 ns OCLK (output) SDO SCKT LRCKT tr tf tsdo tsckt tlrckt OCLK (input) SDO SCKT LRCKT tr tf tsdo tsckt tlrckt toclk thi tlo |
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