STA450A datasheet(20/66 Pages) STMICROELECTRONICS

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STA450A

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HOST_Cmd0

Address

: 0x13

Type

: R/W

Software Reset

: 0

Hardware Reset

: 0

Description

A write into the bits 0 of this register generates a interrupt to the DSP core

HOST_I2cdiv

Address

: 0x1C

Type

: R/W

Software Reset

: 0x0B

Hardware Reset

: 0x0B

Description

Hold time = HOST_I2cdiv/fc where the fc is the DSP system frequency.

HOST_SerialDivH - HOST_SerialDivL

Address

: 0x1F - 0x1E

Type

: R/W

Software Reset

: 0x00(HOST_SerialDivH) - 0x00 (HOST_SerialDivL)

Hardware Reset

: 0x00 (HOST_SerialDivH) - 0x00 (HOST_SerialDivL)

Description

These registers are used to specify the frequency division factor of the system clock for the RS232

interface used for the emulation; bit rate = fc/(( HOST_SerialDivH << 8) | HOST_SerialDivL)

HOST_MemoryAccess

Address

: 0x2B

Type

: W

Software Reset

: NA

Hardware Reset

: 0

Description

Setting the bit 3 the core is enabled to access the ucode inside the memory

7654

3210

Cmd0

7654

3210

Div [5:0]

7654

3210

Div [15:8]

Div[7;0]

7654

3210

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