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STA450A Datasheet(PDF) 62 Page - STMicroelectronics |
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STA450A Datasheet(HTML) 62 Page - STMicroelectronics |
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62 / 66 page  STA450A 62/66 tsckt_max = 6.0 + pad_timing(Cload_SCKT) ns tlrckt_max = 5.5 + pad_timing(Cload_LRCKT) ns tr max = 20 ns tf max = 20 ns 5.2 RESET_N The Reset_N min duration (t_reset_low_min) is 10 us. The RESET_N is active low. 5.3 CLK_IN The CLK_IN typical frequency is 23.92 Mhz. The min high and low time are 5 ns. Trise_clkin max = 16 ns Tfall_clkin max = 16 ns 5.4 Single bit inputs : PCFS, PLL_SYNC The min pulse duration (high or low) on these inputs is 20 ns. Trise max = 20 ns Tfall max = 20 ns 5.5 Single bit outputs : I958_OUT, EVENT_IRQ(GPIO_0), INT1(GPIO_1), INT2(GPIO_2), RESET_N tr tf t_reset_low_min CLK_IN tr tf t_clkin_low_min t_clkin_high_min Internal FIT_*, IT_* at least 1 DSP clk period interrupt sent to DSP core DSP clock PCFS, PLL_SYNC tr tf t_high_min |
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