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STA450A Datasheet(PDF) 63 Page - STMicroelectronics |
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STA450A Datasheet(HTML) 63 Page - STMicroelectronics |
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63 / 66 page ![]() 63/66 STA450A CAP_RST(GPIO_4) PC bitstream interface : USSIO interface in input (PCDC, PCSD) tpcsd_setup_min = 15 ns tpcsd_hold_min = 15 ns tpcdc_min_hi = 20 ns tpcdc_min_low = 20 ns tpcdc_min_period = 60 ns tr_max = 20 ns tf_max = 20 ns 5.6 USSIO in output : Data Port output (DP_EN, DP_DATA, DP_CLK) Notations: Cload_XXX is the load in pF on the XXX output. pad_timing(Cload_XXX) is the propagation delay added to the XXX pad due to the load. The following table gives this timing. t_dpen_max = 6.0 + pad_timing(Cload_DP_EN) - pad_timing(Cload_DP_CLK) Load (pF) max pad_timing (rise) max pad_timing (fall) 25 6 ns 10.6 ns 50 10 ns 13 ns 75 12 ns 15.4 ns 100 14 ns 18 ns I958_OUT, EVENT_IRQ(GPIO_0), tr tf INT1(GPIO_1), INT2(GPIO_2), CAP_RST(GPIO_4) PCDC PCSD tpcsd_setup tpcsd_hold PCDC tpcdc_min_hi t_pcdc_min_low tpcdc_min_period DP_CLK DP_DATA DP_EN tr tf t_dpdata t_dpen |
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