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STA450A

Hardware Reset

: 0

Description

Bit [1:0]

00: no action is performed on the configuration registers of the Level 1.

01: Read action of the configuration registers. During this phase, the content of a selected (by

HOST_pll_add) configuration register of the Level 1 is copied into the HOST_pll_data register.

10: Write action of the configuration registers. During this phase, the content of the

HOST_pll_data

11: do not use.

Bit 2

The bit controls the transfer of the data between the Level 1 and the Level 2 for the System

PLL. When this bit is set, all the registers of the Level 1 (sys_ndiv, sys_pdiv, sys_setupH,

sys_setupL, sys_enable) are copied into the registers of the Level 2 at the same time.

When this bit is cleared, all the Level 2 registers have a stable state independently of the Level

1 registers.

Bit3

Reserved

Bit 4

This bit must be used when switching from one System PLL configuration to the other one.

This bit must be used in conjunction with the bit [2].

HOST_Plladd

Address

: 0x1D

Type

: R/W

Software Reset

: 0

Hardware Reset

: 0

Description

In the follow table the description of the registers addressable by the HOST_Plladd to control the system PLL

7654

3210

Add

Name

Size

Mode

Reset

Comment

pllsys_disable

R - W

System PLL disable control

0 : system PLL enabled

1 : system PLL disabled

pllsys_F_low

R - W

8 low bits of Fractional value for

system PLL

pllsys_F_high

R - W

8 high bits of Fractional value for

system PLL

pllsys_S

R - W

S divider for system PLL

pllsys_N

R - W

N divider for system PLL

pllsys_X

R - W

X divider for system PLL

pllsys_M

R - W

M divider for system PLL

10(0xA)

pllsys_update_frac

R - W

Update Fractional value for

system PLL

12(0xC)

pllsys_paddiv

R - W

pad clock divider

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