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STA450A Datasheet(PDF) 15 Page - STMicroelectronics |
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STA450A Datasheet(HTML) 15 Page - STMicroelectronics |
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15 / 66 page ![]() 15/66 STA450A 2.3 REGISTER MAP The DSP HOST interface includes 256 registers. HOST @ Name Register size Mode SW Reset HW Reset Comment 0x00 HOST_VERSION 8 bits R 0x10 0x10 0x01 HOST_ID 8 bits R 0x20 0x20 0x02 to 0x0F Reserved 0x10 HOST_SOFTRESET 8 bits W NA NA Soft reset of the DSP core and peripherals 0x11 HOST_Plldata 8 bits R – W NC 0 Data register to configure the different configuration registers 0x12 HOST_Pllpcm 3 bits R – W NC 01 PCM clock direction configuration 0x13 HOST_cmd0 1 bit R – W 0 0 I2C Interrupt request 0x14 to 0x17 Reserved 0x18 HOST_Pllcmd 8 bits R – W NC 0 Command register to configure the PLLs 0x19 to 0x1B Reserved 0x1C HOST_I2cdiv 6 bits R – W 0x0B 0x0B Hold time value of the data on SDA versus SCL edges 0x1D HOST_Plladd 8 bits R – W NC 0 Address register to configure the different configuration registers 0x1E HOST_SerialDivL 8 bits R – W 0x00 0x00 RS232 rate coeff L 0x1F HOST_SerialDivH 8 bits R – W 0x00 0x00 RS232 rate coeff H 0x20 to 0x2A Reserved 0x2B Host_Memory Access 4 bits W 0x00 0x00 Enables core to access ucode 0x2C to 0x39 Reserved 0x3A Host_clkstop 1bit W NA 1 Stops the clock to the core 0x3B to 0x3F Reserved 0x40 HOST_SOFTVER 8 bits R – W NA NA Software version (BCD) 0x41 HOST_EVENTINTE0 8 bits R – W NA NA EVENT Interrupt enable bit[7:0] 0x42 HOST_EVENTINTE1 8 bits R – W NA NA EVENT Interrupt enable bit[15:8] 0x43 HOST_EVENTINTE2 8 bits R – W NA NA EVENT Interrupt enable bit[23:16] 0x44 HOST_EVENTINTE3 8 bits R – W NA NA EVENT Interrupt enable bit[31:24] 0x45 HOST_EVENTINT0 8 bits R – W NA NA EVENT Interrupt value bit[7:0] 0x46 HOST_EVENTINT1 8 bits R – W NA NA EVENT Interrupt value bit[15:8] |
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