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STA450A Datasheet(PDF) 16 Page - STMicroelectronics |
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STA450A Datasheet(HTML) 16 Page - STMicroelectronics |
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16 / 66 page  STA450A 16/66 HOST @ Name Register size Mode SW Reset HW Reset Comment 0x47 HOST_EVENTINT2 8 bits R – W NA NA EVENT Interrupt value bit[23:16] 0x48 HOST_EVENTINT3 8 bits R – W NA NA EVENT Interrupt value bit[31:24] 0x49 HOST_ERRINTEL 8 bits R – W NA NA ERROR Interrupt enable bit[7:0] 0x4A HOST_ERRINTEH 8 bits R – W NA NA ERROR Interrupt enable bit[15:8] 0x4B HOST_ERRINTL 8 bits R – W NA NA ERROR Interrupt value bit[7:0] 0x4C HOST_ERRINTH 8 bits R – W NA NA ERROR Interrupt value bit[15:8] 0x4D HOST_STARTUP 8 bits R – W NA NA Startup 0x4E HOST_PCMDIV 8 bits R – W NA NA Pcm clock divider 0x4F HOST_PCMCNF 8 bits R – W NA NA Pcm Configuration 0x50 HOST_APLL48_LSB (1) 8 bits R – W NA NA Fractional PLL LSB reference value for Fs = 48KHz family 0x51 HOST_APLL48_MSB(1) 8 bits R – W NA NA Fractional PLL MSB reference value for Fs = 48KHz family 0x52 HOST_APLL48_XDIV(1) 8 bits R – W NA NA Fractional PLL X Divider for Fs = 48KHz family 0x53 HOST_APLL48_MDIV(1) 8 bits R – W NA NA Fractional PLL M Divider for Fs = 48KHz family 0x54 HOST_APLL48_NDIV(1) 8 bits R – W NA NA Fractional PLL N Divider for Fs = 48KHz family 0x55 HOST_APLL441_LSB(1) 8 bits R – W NA NA Fractional PLL LSB reference value for Fs = 44.1KHz family 0x56 HOST_APLL441_MSB(1) 8 bits R – W NA NA Fractional PLL MSB reference value for Fs = 44.1KHz family 0x57 HOST_APLL441_XDIV(1) 8 bits R – W NA NA Fractional PLL X Divider for Fs = 44.1KHz family 0x58 HOST_APLL441_MDIV(1) 8 bits R – W NA NA Fractional PLL M Divider for Fs = 44.1KHz family 0x59 HOST_APLL441_NDIV(1) 8 bits R – W NA NA Fractional PLL N Divider for Fs = 44.1KHz family 0x5A ENABLE_IT432 8 bits R – W NA NA Enable control with FRAC PLL 0x5B IT432_CONF 8 bits R – W NA NA Edge configuration for IT432 0x5C HOST_MaxDev 8 bits R – W NA NA Hax duration windows divider factor 0x5D HOST_Decoder BitRate 8 bits R – W NA NA Active Audio decoder bitrate 0x5E HOST_Bitstream Synchro 8 bits R – W NA NA Synchronization 0x5F Host_DataPort_BitRate 8 bits R – W NA NA Data Port Bit Rate 0x60 to 0x65 Reserved 0x66 HOST_EVENTINTE4 8 bits R – W NA NA EVENT interrupt enable bit [7:0] |
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