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MPC5675KFF0VMS2R Datasheet(PDF) 110 Page - NXP Semiconductors |
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MPC5675KFF0VMS2R Datasheet(HTML) 110 Page - NXP Semiconductors |
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110 / 147 page  MPC5675K Microcontroller Data Sheet, Rev. 9 Electrical characteristics NXP Semiconductors 110 Figure 25. DDR AC test load 3.22.2 IEEE 1149.1 (JTAG) interface timing 3.22.2.1 Standard interface timing 3.22.2.2 Interface timing for Full Cycle mode Table 62. JTAG pin AC electrical characteristics No. Symbol Parameter Conditions Min Max Unit 1tJCYC D TCK cycle time 1 1 f TCK =1/tTCK. fTCK must not exceed 1/4 the frequency of the system clock (SYS_CLK). —60 — ns 2tJDC D TCK clock pulse width (measured at VDDE/2) — 40 60 % 3tTCKRISE D TCK rise and fall times (40%–70%) — — 3 ns 4tTMSS, tTDIS D TMS, TDI data setup time — 12 — ns 5tTMSH, tTDIH D TMS, TDI data hold time — 6 — ns 6tTDOV D TCK low to TDO data valid — — 18 ns 7tTDOI D TCK low to TDO data invalid — 6 — ns 8tTDOHZ D TCK low to TDO high impedance — — 18 ns 9tBSDV D TCK falling edge to output valid (BSR) — — 14 ns 10 tBSDVZ D TCK falling edge to output valid out of high impedance (BSR) —— 15 ns 11 tBSDHZ D TCK falling edge to output high impedance (BSR) — — 10 ns 12 tBSDST D Boundary scan input valid to TCK rising edge — 15 — ns 13 tBSDHT D TCK rising edge to boundary scan input invalid — 2 — ns Table 63. JTAG pin Full Cycle mode AC electrical characteristics No. Symbol Parameter Conditions Min Max Unit 1tJCYC D TCK cycle time 1 —40 — ns 2tJDC D TCK clock pulse width (measured at VDDE/2) — 40 60 % 3tTCKRISE D TCK rise and fall times (40%–70%) — — 3 ns 4tTMSS, tTDIS D TMS, TDI data setup time — 12 — ns 5tTMSH, tTDIH D TMS, TDI data hold time — 6 — ns 6tTDOV D TCK low to TDO data valid — — 18 ns 7tTDOI D TCK low to TDO data invalid — 6 — ns Output Z0 =50 Ω RL = 50 Ω VDD_MEM_IO/2 |
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