MPC5675KFF0VMS2R datasheet(113/147 Pages) NXP

113 / 147 page

Electrical characteristics

MPC5675K Microcontroller Data Sheet, Rev. 9

NXP Semiconductors

113

Figure 29. Nexus SDR (Even divisor) timing

Figure 30. Nexus SDR output timing for DIV=3

Table 65. Nexus debug port timing Divide by 3 SDR mode1

1 MDO, MSEO, and EVTO data is held valid until next MCKO low cycle in SDR mode. Rise/Fall time for Nexus signals

can be derived from Fast GPIO pad specification section.

No.

Symbol

Parameter

Conditions

Min

Max

Unit

1tMCKO

CC MCKO cycle time

—

16.67

—

2tMDC

CC MCKO duty cycle2

2 Jitter/tolerance for MCKO clock is derived from PLL. Please see PLL section for jitter specification.

—33

3tMDOV

CC MCKO Low to MDO, MSEO, EVTO data valid

—

–1.67

3.34

4tEVTIPW

CC EVTI pulse width. Captured on JTAG TCK.

—

4.0

—

tJCYC

5tPW

CC MDO, MSEO,EVTO pulse width in SDR mode

—

tMCKO

MCKO

MDO

MSEO

EVTO

Output Data Valid

EVTI

MCKO

MDO

MSEO

EVTO

Output Data Valid

EVTI

MPC5675KFF0VMS2R Datasheet(PDF) 113 Page - NXP Semiconductors

MPC5675KFF0VMS2R Datasheet(HTML) 113 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL