MPC5675KFF0VMS2R datasheet(112/147 Pages) NXP

112 / 147 page

MPC5675K Microcontroller Data Sheet, Rev. 9

Electrical characteristics

NXP Semiconductors

112

Figure 28. JTAG boundary scan timing

3.22.3

Nexus timing

Table 64. Nexus debug port timing Div mode = 21

1 All Nexus timing relative to MCKO is measured from 50% of MCKO and 50% of the respective signal. Rise/Fall time

for Nexus signals can be derived from Fast GPIO pad specification section.

No.

Symbol

Parameter

Conditions

Min

Max

Unit

1tMCKO

CC MCKO cycle time

—

16.67

—

2tMDC

CC MCKO duty cycle2

2 Jitter/tolerance for MCKO clock is derived from PLL. Please see PLL section for jitter specification.

—50

3tMDOV

CC MCKO Low to MDO, MSEO, EVTO data valid3

3 MDO, MSEO, and EVTO data is held valid until next MCKO low cycle in SDR mode. For DDR mode, this timing is

same for both MCKO edges.

—

–1.67

3.34

4tEVTIPW

CC EVTI pulse width. Captured on JTAG TCK.

—

4.0

—

tJCYC

5tPW

CC MDO, MSEO,EVTO pulse width in SDR mode

—

tMCKO

TCK

Output

Signals

Input

Signals

Output

Signals

MPC5675KFF0VMS2R Datasheet(PDF) 112 Page - NXP Semiconductors

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