MPC8308CVMADDA datasheet(4/95 Pages) NXP

4 / 95 page

MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4

Freescale Semiconductor

Electrical Characteristics

Table 2. Recommended operating conditions

Characteristic

Symbol

Recommended Value1

1 GV

DD, NVDD, AVDD, and VDD must track each other and must vary in the same direction—either in the positive or negative

direction.

Unit

SerDes internal digital power

XCOREVDD

1.0 V ± 50 mV

SerDes internal digital power

XCOREVSS

0.0

SerDes I/O digital power

XPADVDD

1.0 V ± 50 mV

SerDes analog power for PLL

SDAVDD

1.0 V ± 50 mV

SerDes analog power for PLL

SDAVSS

SerDes I/O digital power

XPADVSS

Core supply voltage

VDD

1.0V±50mV

Analog supply for e300 core APLL2

2 This voltage is the input to the filter discussed in Section 23.2, “PLL Power Supply Filtering,” and not necessarily the voltage

at the AVDD pin, which may be reduced from VDD by the filter.

AVDD1

1.0V±50mV

Analog supply for system APLL2

AVDD2

1.0V±50mV

DDR2 DRAM I/O voltage

GVDD

1.8 V ± 100 mV

Differential reference voltage for DDR controller

MVREF

GVDD/2 (0.49

 GV

DD to

0.51

 GV

DD)

Standard I/O voltage (Local bus, DUART, system control and power

management, eSDHC, USB, I2C, Interrupt, Ethernet management,

SPI, Miscellaneous and JTAG I/O voltage)3

3 NV

DD here refers to NVDDA, NVDDB,NVDDG, NVDDH, NVDDJ and NVDDP_K from the ball map.

NVDD

3.3 V ± 300 mV

eTSEC IO supply4,5

4 The max value of supply voltage should be selected based on the RGMII mode. The lower range applies to RGMII mode.

5 LV

DD1 here refers to NVDDC and LVDD2 refers to NVDDF from the ball map.

LVDD1, LVDD2

2.5 V ± 125 mV

3.3 V ± 300 mV

Analog and digital ground

VSS

0.0

Operating temperature range6

6 Minimum temperature is specified with T

A; Maximum temperature is specified with TJ.

TA/TJ

Standard = 0 to 105

Extended = -40 to 105

C

Notes:

MPC8308CVMADDA Datasheet(PDF) 4 Page - NXP Semiconductors

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