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MPC8308CVMADDA Datasheet(PDF) 53 Page - NXP Semiconductors

Part # MPC8308CVMADDA
Description  MPC8308 PowerQUICC II Pro Processor Hardware Specification
PDF  95 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

MPC8308CVMADDA Datasheet(HTML) 53 Page - NXP Semiconductors

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MPC8308 PowerQUICC II Pro Processor Hardware Specification, Rev. 4
Freescale Semiconductor
53
I2C
15 I2C
This section describes the DC and AC electrical characteristics for the I2C interface.
15.1
I2C DC Electrical Characteristics
This table provides the DC electrical characteristics for the I2C interface.
15.2
I2C AC Electrical Specifications
This table provides the AC timing parameters for the I2C interface.
Table 43. I2C DC Electrical Characteristics
At recommended operating conditions with NVDD of 3.3 V ± 0.3 V.
Parameter
Symbol
Min
Max
Unit Notes
Input high voltage level
VIH
0.7
 NV
DD
NVDD + 0.3
V
—
Input low voltage level
VIL
–0.3
0.3
 NV
DD
V—
Low level output voltage
VOL
00.2
 NV
DD
V1
High level output voltage
VOH
0.8 x NVDD
NVDD + 0.3
V
—
Output fall time from VIH(min) to VIL(max) with a bus capacitance from 10
to 400 pF
tI2KLKV 20 + 0.1  CB
250
ns
2
Pulse width of spikes which must be suppressed by the input filter
tI2KHKL
050
ns
3
Capacitance for each I/O pin
CI
—10
pF
—
Input current, (0 V
V
IN NVDD)IIN
—± 5
A—
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. CB = capacitance of one bus line in pF.
3. For information on the digital filter used, see the MPC8308 PowerQUICC II Pro Processor Reference Manual.
Table 44. I2C AC Electrical Specifications
All values refer to VIH (min) and VIL (max) levels (see Table 43).
Parameter
Symbol1
Min
Max
Unit
SCL clock frequency
fI2C
0
400
kHz
Low period of the SCL clock
tI2CL
1.3
—
s
High period of the SCL clock
tI2CH
0.6
—
s
Setup time for a repeated START condition
tI2SVKH
0.6
—
s
Hold time (repeated) START condition (after this period, the first clock pulse is generated)
tI2SXKL
0.6
—
s
Data setup time
tI2DVKH
100
—
ns
Data hold time:
I2C bus devices
tI2DXKL
—
0 2
—
0.9 3
s
Fall time of both SDA and SCL signals5
tI2CF
—300
ns



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