NRF9160-SICA-R7 datasheet(292/400 Pages) NORDIC

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Peripherals

6.17.1 Shared resources

The TWI master shares registers and other resources with other peripherals that have the same ID as the

TWI master. Therefore, you must disable all peripherals that have the same ID as the TWI master before

the TWI master can be configured and used.

Disabling a peripheral that has the same ID as the TWI master will not reset any of the registers that are

shared with the TWI master. It is therefore important to configure all relevant registers explicitly to secure

that the TWI master operates correctly.

The Instantiation table in Instantiation on page 24 shows which peripherals have the same ID as the TWI.

6.17.2 EasyDMA

The TWIM implements EasyDMA for accessing RAM without CPU involvement.

The TWIM peripheral implements the EasyDMA channels found in the following table.

Channel

Type

TXD

READER

TXD

RXD

WRITER

RXD

Table 89: TWIM EasyDMA Channels

For detailed information regarding the use of EasyDMA, see EasyDMA on page 45.

The .PTR and .MAXCNT registers are double-buffered. They can be updated and prepared for the next RX/

TX transmission immediately after having received the RXSTARTED/TXSTARTED event.

The STOPPED event indicates that EasyDMA has finished accessing the buffer in RAM.

6.17.3 Master write sequence

A TWI master write sequence is started by triggering the STARTTX task. After the STARTTX task has been

triggered, the TWI master will generate a start condition on the TWI bus, followed by clocking out the

address and the READ/WRITE bit set to 0 (WRITE=0, READ=1).

The address must match the address of the slave device that the master wants to write to. The READ/

WRITE bit is followed by an ACK/NACK bit (ACK=0 or NACK=1) generated by the slave.

After receiving the ACK bit, the TWI master will clock out the data bytes found in the transmit buffer

located in RAM at the address specified in the TXD.PTR register. Each byte clocked out from the master will

be followed by an ACK/NACK bit clocked in from the slave.

A typical TWI master write sequence is shown in the following figure. Occurrence 2 in the figure illustrates

clock stretching performed by the TWI master following a SUSPEND task.

A SUSPENDED event indicates that the SUSPEND task has taken effect. This event can be used to

synchronize the software.

The TWI master will generate a LASTTX event when it starts to transmit the last byte, this is shown in the

following figure.

4418_1315 v2.0

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