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NRF9160-SICA-R7 Datasheet(PDF) 355 Page - Nordic Semiconductor

Part # NRF9160-SICA-R7
Description  nRF9160 Product Specification
PDF  400 Pages
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Manufacturer  NORDIC [Nordic Semiconductor]
Direct Link  https://www.nordicsemi.com/
Logo NORDIC - Nordic Semiconductor

NRF9160-SICA-R7 Datasheet(HTML) 355 Page - Nordic Semiconductor

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Peripherals
6.20.2 Temporarily pausing the watchdog
By default, the watchdog will be active counting down the down-counter while the CPU is sleeping and
when it is halted by the debugger. It is however possible to configure the watchdog to automatically pause
while the CPU is sleeping as well as when it is halted by the debugger.
6.20.3 Watchdog reset
A TIMEOUT event will automatically lead to a watchdog reset.
See Reset on page 56 for more information about reset sources. If the watchdog is configured to generate
an interrupt on the TIMEOUT event, the watchdog reset will be postponed with two 32.768 kHz clock
cycles after the TIMEOUT event has been generated. Once the TIMEOUT event has been generated, the
impending watchdog reset will always be effectuated.
The watchdog must be configured before it is started. After it is started, the watchdog’s configuration
registers, which comprise registers CRV, RREN, and CONFIG, will be blocked for further configuration.
The watchdog can be reset from several reset sources, see Reset behavior on page 57.
When the device starts running again, after a reset, or waking up from OFF mode, the watchdog
configuration registers will be available for configuration again.
6.20.4 Registers
Base address Peripheral
Instance
Secure mapping
DMA security
Description
Configuration
0x50018000
0x40018000
WDT
WDT : S
WDT : NS
US
NA
Watchdog timer
Table 101: Instances
Register
Offset
Security Description
TASKS_START
0x000
Start the watchdog
SUBSCRIBE_START
0x080
Subscribe configuration for task START
EVENTS_TIMEOUT
0x100
Watchdog timeout
PUBLISH_TIMEOUT
0x180
Publish configuration for event TIMEOUT
INTENSET
0x304
Enable interrupt
INTENCLR
0x308
Disable interrupt
RUNSTATUS
0x400
Run status
REQSTATUS
0x404
Request status
CRV
0x504
Counter reload value
RREN
0x508
Enable register for reload request registers
CONFIG
0x50C
Configuration register
RR[n]
0x600
Reload request n
Table 102: Register overview
6.20.4.1 TASKS_START
Address offset: 0x000
Start the watchdog
4418_1315 v2.0
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