STM32U5A5QJ datasheet(334/382 Pages) STMICROELECTRONICS

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Electrical characteristics

STM32U5Axxx

334/382

DS13543 Rev 1

5.3.36

HSPI characteristics

Unless otherwise specified, the parameters given in the table below are derived from tests

performed under the ambient temperature, fAHB frequency and VDD supply voltage

conditions summarized in Table 33, with the following configuration:

•

Output speed set to OSPEEDRy[1:0] = 11

•

Measurement points done at 0.5 × VDD level

•

I/O compensation cell activated

•

HSLV activated when VDD ≤ 2.7 V

•

Voltage scaling range 1 unless otherwise specified

Refer to Section 5.3.14: I/O port characteristics for more details on the input/output alternate

function characteristics.

5.3.37

SD/SDIO/e•MMC card host interfaces (SDMMC) characteristics

Unless otherwise specified, the parameters given in Table 142 and Table 143 are derived

from tests performed under the ambient temperature, fAHB frequency and VDD supply

voltage conditions summarized in Table 33, with the following configuration:

•

Output speed set to OSPEEDRy[1:0] = 10

•

Capacitive load CL = 30 pF, unless otherwise specified

•

Measurement points done at 0.5 × VDD level

•

I/O compensation cell activated

•

HSLV activated when VDD ≤ 2.7 V

•

Voltage scaling range 1

Refer to Section 5.3.14: I/O port characteristics for more details on the input/output

characteristics.

Table 142. SD/e•MMC characteristics (VDD = 2.7 V to 3.6 V)(1)(2)

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

fPP

Clock frequency in data transfer mode

100(3)

MHz

tW(CKL)

Clock low time

fPP = 52 MHz

8.5

9.5

tW(CKH)

Clock high time

fPP = 52 MHz

8.5

9.5

CMD, D inputs (referenced to CK) in e•MMC legacy/SDR/DDR and SD HS/SDR(4)/DDR(4) modes

tISU

Input setup time HS

3.5

tIH

Input hold time HS

1.5

tIDW(5)

Input valid window (variable window)

4.5

CMD, D outputs (referenced to CK) in e•MMC legacy/SDR/DDR and SD HS/SDR(4)/DDR(4) modes

tOV

Output valid time HS

6.5

7.5/8.5

(6)

tOH

Output hold time HS

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