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STM32U5A5QJ Datasheet(PDF) 338 Page - STMicroelectronics

Part # STM32U5A5QJ
Description  Ultra-low-power Arm® Cortex®-M33 32-bit MCUTrustZone®FPU,240 DMIPS, 4 MB Flash, 2.5 MB SRAM, LTDC, MIPI® DSI, crypto
PDF  382 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STM32U5A5QJ Datasheet(HTML) 338 Page - STMicroelectronics

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Electrical characteristics
STM32U5Axxx
338/382
DS13543 Rev 1
Figure 76. USART timing diagram in master mode
Table 146. USART characteristics(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fCK
USART clock
frequency
Master mode, 1.71 V ≤ VDDIOX ≤ 3.6 V
-
-
20
MHz
Slave receiver, 1.71 V ≤ VDDIOX ≤ 3.6 V
-
-
53
Slave transmitter, 1.71 V ≤ VDDIOX ≤ 3.6 V
-
-
27
Slave transmitter, 2.7 V ≤ VDDIOX ≤ 3.6 V
-
-
30
tsu(NSS) NSS setup time Slave mode
Tker(2) + 2
-
-
ns
th(NSS) NSS hold time Slave mode
2
-
-
tw(CKH)
tw(CKL)
CK high and
low time
Master mode
1/fCK / 2 - 1 1/fCK / 2 1/fCK / 2 + 1
tsu(RX) Data input
setup time
Master mode
15
-
-
tsu(TX)
Slave mode
2.5
-
-
th(RX) Data input hold
time
Master mode
4
-
-
th(RX)
Slave mode
1
-
-
tv(TX)
Data output
valid time
Slave mode, 2.7 V ≤ VDDIOX ≤ 3.6 V
-
13
16.5
Slave mode, 1.71 V ≤ VDDIOX ≤ 3.6 V
-
13
18.5
tv(TX)
Master mode
-
2.5
6.5
th(TX)
Data output
hold time
Slave mode
8.5
-
-
th(TX)
Master mode
0.5
-
-
1. Evaluated by characterization. Not tested in production.
2. Tker is the usart_ker_ck_pres clock period.
MSv65386V4
CPHA = 0
TX
OUTPUT
RX
INPUT
CPHA = 0
LSB OUT
LSB IN
CPOL = 0
CPOL = 1
BIT1 OUT
1/fCK
tw(CKH)
tw(CKL)
th(RX)
CPHA = 1
CPHA = 1
CPOL = 0
CPOL = 1
tsu(RX)
tv(TX)
th(TX)
MSB IN
BIT6 IN
MSB OUT



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