DSP56321RMSLASHD datasheet(48/88 Pages) NXP

48 / 88 page

2-24

AC Electrical Characteristics

2.5.8

ESSI0/ESSI1 Timing

Table 2-12. ESSI Timings

No.

Characteristics4, 6

Symbol

Expression

220 MHz

240 MHz

Cond-

ition5

Unit

Min Max Min Max

430

Clock cycle1

TECCX

TECCI

× T

27.3

36.4

—

25.0

33.3

—

x ck

i ck

431

Clock high period

•

For external clock

•

For internal clock

TECCX/2 − 10.0

TECCI/2 − 10.0

3.7

8.2

—

2.5

6.7

—

x ck

i ck

432

Clock low period

•

For external clock

•

For internal clock

TECCX/2 − 10.0

TECCI/2 − 10.0

3.7

8.2

—

2.5

6.7

—

x ck

i ck

433

RXC rising edge to FSR out (bit-length) high

0.25

× T

ECCX

0.25

× T

ECCI

—

6.8

9.1

—

6.3

8.3

x ck

i ck a

434

RXC rising edge to FSR out (bit-length) low

0.25

× T

ECCX

0.25

× T

ECCI

—

6.8

9.1

—

6.3

8.3

x ck

i ck a

435

RXC rising edge to FSR out (word-length-relative)

high2

0.25

× T

ECCX

0.25

× T

ECCI

—

6.8

9.1

—

6.3

8.3

x ck

i ck a

436

RXC rising edge to FSR out (word-length-relative)

low2

0.25

× T

ECCX

0.25

× T

ECCI

—

6.8

9.1

—

6.3

8.3

x ck

i ck a

437

RXC rising edge to FSR out (word-length) high

0.25

× T

ECCX

0.25

× T

ECCI

—

6.8

9.1

—

6.3

8.3

x ck

i ck a

438

RXC rising edge to FSR out (word-length) low

0.25

× T

ECCX

0.25

× T

ECCI

—

6.8

9.1

—

6.3

8.3

x ck

i ck a

439

Data in setup time before RXC (SCK in

Synchronous mode) falling edge

0.2

× T

ECCX

0.2

× T

ECCI

5.5

7.3

—

6.7

—

x ck

i ck

440

Data in hold time after RXC falling edge

0.15

× T

ECCX

0.15

× T

ECCI

4.1

5.5

—

3.8

5.0

—

x ck

i ck

441

FSR input (bl, wr) high before RXC falling edge2

0.2

× T

ECCX

0.2

× T

ECCI

5.5

7.3

—

6.7

—

x ck

i ck a

442

FSR input (wl) high before RXC falling edge

0.2

× T

ECCX

0.2

× T

ECCI

5.5

7.3

—

6.7

—

x ck

i ck a

443

FSR input hold time after RXC falling edge

0.15

× T

ECCX

0.15

× T

ECCI

4.1

5.5

—

3.8

5.0

—

x ck

i ck a

444

Flags input setup before RXC falling edge

0.2

× T

ECCX

0.2

× T

ECCI

5.5

7.3

—

6.7

—

x ck

i ck s

445

Flags input hold time after RXC falling edge

0.15

× T

ECCX

0.15

× T

ECCI

4.1

5.5

—

3.8

5.0

—

x ck

i ck s

446

TXC rising edge to FST out (bit-length) high

0.25

× T

ECCX

0.25

× T

ECCI

—

6.8

9.1

—

6.3

8.3

x ck

i ck

447

TXC rising edge to FST out (bit-length) low

0.25

× T

ECCX

0.25

× T

ECCI

—

6.8

9.1

—

6.3

8.3

x ck

i ck

448

TXC rising edge to FST out (word-length-relative)

high2

0.25

× T

ECCX

0.25

× T

ECCI

—

6.8

9.1

—

6.3

8.3

x ck

i ck

449

TXC rising edge to FST out (word-length-relative)

low2

0.25

× T

ECCX

0.25

× T

ECCI

—

6.8

9.1

—

6.3

8.3

x ck

i ck

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

DSP56321RM/D Datasheet(PDF) 48 Page - NXP Semiconductors

DSP56321RM/D Datasheet(HTML) 48 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

Datasheet Download

Link URL