DSP56321RMSLASHD datasheet(53/88 Pages) NXP

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AC Electrical Characteristics

2.5.10

CONSIDERATIONS FOR GPIO USE

The following considerations can be helpful when GPIO is used.

2.5.10.1 GPIO as Output

• The time from fetch of the instruction that changes the GPIO pin to the actual change is seven core

clock cycles, if the instruction is a one-cycle instruction and there are no pipeline stalls or any other

pipeline delays.

• The maximum rise or fall time of a GPIO pin is 13 ns (TTL levels, assuming that the maximum of 50

pF load limit is met).

2.5.10.2 GPIO as Input

GPIO inputs are not synchronized with the core clock. When only one GPIO bit is polled, this lack of

synchronization presents no problem, since the read value can be either the previous value or the new

value of the corresponding GPIO pin. However, there is the risk of reading an intermediate state if:

• Two or more GPIO bits are treated as a coupled group (for example, four possible status states encoded

in two bits).

• The read operation occurs during a simultaneous change of GPIO pins (for example, the change of 00

to 11 may happen through an intermediate state of 01 or 10).

Therefore, when GPIO bits are read, the recommended practice is to poll continuously until two

consecutive read operations have identical results.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

DSP56321RM/D Datasheet(PDF) 53 Page - NXP Semiconductors