DSP56321RMSLASHD datasheet(12/88 Pages) NXP

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1-6

External Memory Expansion Port (Port A)

Input

Ignored Input

Bus Grant—Asserted by an external bus arbitration circuit when the

DSP56321T becomes the next bus master. When BG is asserted, the

DSP56321T must wait until BB is deasserted before taking bus

mastership. When BG is deasserted, bus mastership is typically given

up at the end of the current bus cycle. This may occur in the middle of an

instruction that requires more than one external bus cycle for execution.

To ensure proper operation, the user must set the asynchronous bus

arbitration enable (ABE) bit (Bit 13) in the Operating Mode Register.

When this bit is set, BG and BB are synchronized internally. This adds a

required delay between the deassertion of an initial BG input and the

assertion of a subsequent BG input.

Input/

Output

Ignored Input

Bus Busy—Indicates that the bus is active. Only after BB is deasserted

can the pending bus master become the bus master (and then assert

the signal again). The bus master may keep BB asserted after ceasing

bus activity regardless of whether BR is asserted or deasserted. Called

“bus parking,” this allows the current bus master to reuse the bus

without rearbitration until another device requires the bus. BB is

deasserted by an “active pull-up” method (that is, BB is driven high and

then released and held high by an external pull-up resistor).

Notes:

See BG for additional information.

BB requires an external pull-up resistor.

Table 1-7. External Bus Control Signals (Continued)

Signal

Name

Type

State During

Reset, Stop, or

Wait

Signal Description

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

DSP56321RM/D Datasheet(PDF) 12 Page - NXP Semiconductors