HMLQ25201T-R47MSR datasheet(29/52 Pages) RENESAS

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DA9080

High Current, Highly Configurable System

PMIC with Four Bucks and One LDO

Datasheet

Revision 1.2

08-Feb-2022

CFR0011-120-00

29 of 51

Supervision

8.1

Input Voltage Monitor Flag

The voltage at the VSYS pin is continually monitored. The status of this pin is reported in a 2-bit

when the voltage on the VSYS pin transitions below 4.4 V. The input voltage monitor comparator has

a 4.6 V rise, 4.4 V fall, and 0.2 V hysteresis. The host can poll these two bits to check the status of

this pin. The sticky bit is cleared by writing 1 to it.

8.2

Fault Protection

8.2.1

Over-Voltage, Under-Voltage, and Over-Current Protection

Each buck has over-voltage (OV), under-voltage (UV), and over-current (OC) fault protection.

When the buck output drops below VTHR_UVP_FALL, the BUCK<x>_UV_STAT bit in the PMC_CH_UV

bit in the PMC_CH_OV register is set to 0x1.

Each of the bucks has current limit, IPOSLIM, with programmable thresholds. When the current limit is

met, the BUCK<x>_OC_STAT bit in the PMC_CH_OC register is set to 0x1.

The LDO has under-voltage (UV) and over-current (OC) fault protection. When either of these

conditions is met, status bits are set to 0x1 in dedicated registers, in a similar way to the bucks. A

supply voltage fault condition (UV or OV), on any supply, causes an immediate power down and all

supplies are disabled. The sequencer will not run and the supplies will not perform a controlled ramp-

down of the output voltage.

A re-start is initiated, after a blanking time, with a hiccup behavior. The outputs are discharged by the

internal pull-down resistors prior to being enabled again.

The UV, OV and OC register bits are sticky and remain set through a hiccup cycle, see Figure 10.

The register bits are only cleared on a register write of 1.

8.2.2

Thermal Shutdown

DA9080 also has a thermal shutdown (TSD) function. When the die temperature goes above 140 °C

(typ) (TTHR_SHDN), all the regulator outputs and the GPADC are immediately shutdown. The TSD event

is recorded in a register OVERTEMP_EVENT bit<7> in PMC_CH_OC (0x01).

When the die temperature goes below 125 °C(typ), the start-up sequence is restarted.

Note that the I2C communication is halted during TSD, the OVERTEMP_EVENT bit cannot be read

back at this time. The host should check the OVERTEMP_EVENT bit after the device has recovered

from TSD. The OVERTEMP_EVENT bit is sticky and is cleared by over-writing the bit with 1.

HMLQ25201T-R47MSR Datasheet(PDF) 29 Page - Renesas Technology Corp

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