ZAMC4100GA2R datasheet(30/156 Pages) RENESAS

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ZAMC4100 Datasheet

January 26, 2016

2.7.

LIN Interface

The ZAMC4100 features a LIN slave interface with hardware resources covering the physical and data link

communication layers (see Figure 2.2). The network layer must be implemented as part of the MCU firmware.

The LIN PHY is built into the SBC chip and is LIN2.0/2.1 compatible. It supports LIN wake-up detection, short-

circuit detection/protection and dominant time-out detection/protection. All events are captured as interrupt flags in

the SBC interrupt controller, and the MCU can access them via the SPI interface.

Figure 2.2 ZAMC4100 LIN Interface and Open Systems Interconnection (OSI) Layers Coverage

SBC: LIN PHY,

Wake-up, Diagnostics

MCU: LIN Controller

MCU: Firmware

(LIN Protocol Engine)

PHYSICAL

Media, Signal & Binary

Transmission

DATA LINK

Physical Addressing

NETWORK

Path Determination &

Logical Addressing

BITS

FRAMES

PACKETS

OSI Model

The block diagram in Figure 2.3 shows the ZAMC4100 LIN interface structure and the partitioning between the

SBC and MCU chips. The hardware for covering the LIN data link layer is implemented in the MCU chip as a LIN

controller. The MCU LIN controller features a UART module for the LIN frame generation, BREAK/SYNC

detection fields, and LIN bus inactivity timer.

Figure 2.3 LIN Slave Node Implementation in the ZAMC4100

RXD

TXD

LIN

LIN PHY

TXD

RXD

LIN Wake-up

Diag & Ctrl

Dominant

Time-Out

LIN Short

(debounced)

LIN Wake-up

LIN Pwr Crtl

LIN Controller

BREAK/SYNC

Detection

Inactivity Timer

(4 sec)

SBC Chip

MCU Chip

UART

sh = short

pd = power down

ZAMC4100GA2R Datasheet(PDF) 30 Page - Renesas Technology Corp

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