ZAMC4100GA2R datasheet(66/156 Pages) RENESAS

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ZAMC4100 Datasheet

January 26, 2016

3.9.1.

High-Side Control and Status Register

Table 3.20 HSDCTRL Register Bits Mapping

Name

HSDCTRL

Bit No

Bit name

Reset

Access

R/W

Address

0x08

R/W = Read/Write

Table 3.21 HSDCTRL Register Bits Description

Bit

Description

7:4

HSxCSEN:

1), 2) Current source enable bit for high-side driver x, (x = 4 to 1).

1 = The current source of high-side driver x is enabled.

0 = The current source of high-side driver x is disabled.

3:0

HSxEN:

2), 3), 4) High-side driver enable.

1 = High-side driver x (x = 4 to 1) enabled.

0 = High-side driver x (x = 4 to 1) disabled.

Note: Bits HSxEN are automatically cleared at SLEEP or STANDBY Mode entry.

To keep current consumption as low as possible, the MCU software should disable the current sources before enabling the SLEEP or STANDBY Modes.

These bits are automatically cleared in the event of an over-temperature event.

Bits HSxEN are automatically cleared at SLEEP or STANDBY Mode entry.

These bits are gated if failure event (OVT, OC, OV, UV, CPVE) is captured in interrupt flag (see Figure 3.14).

3.9.2.

High-Side Over-Current Protection

The high-side over-current protection circuitry is identical to the protection for the half-bridge driver previously

discussed in section 3.8.2.

3.9.3.

High-Side Drivers Output Diagnostic Check

Each high-side driver has a dedicated diagnostic circuitry that is able to detect an open/short failure in the output

load. The diagnostic functionality is controlled and monitored respectively by registers HSDCTRL (Table 3.20 and

Table 3.21) and HSDSTAT (Table 3.22 and Table 3.23). Table 3.24 gives the meaning of the HSxOSF flags in the

HSDSTAT register with respect to the value of bit HSxCSEN in the HSDCTRL register, which controls the

corresponding diagnostic current source.

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