ZAMC4100GA2R datasheet(50/156 Pages) RENESAS

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ZAMC4100 Datasheet

January 26, 2016

3.6.1.

SBC Interrupts: Enabling, Flagging, and Clearing Procedure

Each SBC global interrupt source has an individual interrupt enable (IE) bit. If an interrupt is enabled and the

interrupt event occurs, it affects the IRQN line by forcing it to low. On power-on-reset all interrupts are disabled.

All interrupt sources are continuously observed during the system operation. If an interrupt event occurs, it is

detected and indicated by setting the corresponding interrupt flag (IF) bit to ‘1,’ which remains high until the MCU

clears it. The interrupt events are detected and the corresponding interrupt flag is set even if the interrupt is

disabled.

Each interrupt flag can be cleared by the MCU. In order to clear an interrupt, the MCU should write a logic ‘1’ into

its flag bit. This is a dummy write that is executed by the SBC as an IF clearing. In order to clear a global interrupt

flag, the MCU must clear all peripheral interrupts belonging to the global flag. If the MCU executes the interrupt

clearing procedure but the interrupt event is still present, the flag will not be cleared.

The ADCRDYIF flag (Table 3.12) supports a second clearing method, which is reading the ADC result register

(see section 3.12.8). Another exception is the WDTIF watchdog interrupt, which is cleared by clearing the WDT

(Table 3.4).

3.6.2.

SBC Global Interrupts Registers

The SBC registers used for global interrupt enabling and reading are IRQCTRL and IRQSTAT. All global interrupt

enable and flag bits are given in Table 3.7 and

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