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ZAMC4100GA2R Datasheet(PDF) 82 Page - Renesas Technology Corp |
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ZAMC4100GA2R Datasheet(HTML) 82 Page - Renesas Technology Corp |
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82 / 156 page  ZAMC4100 Datasheet © 2016 Integrated Device Technology, Inc. 82 January 26, 2016 Table 3.34 ADCCTRL Register Bits Mapping Name ADCCTRL Bit No 7 6 5 4 3 2 1 0 Bit name Reset U 0 0 0 0 0 0 0 Access U R/W R/W R/W R/W R/W R/W R/W Address 0x12 R/W = Read/Write bit; U = Unimplemented, read as ‘0.’ Note: When the ADC conversion is running, bits INPSEL[4:0] are accessed as read-only. Table 3.35 ADCCTRL Register Bits Description Bit Description 7 Unimplemented bit. Read as 0. 6 CCNV: Continuous Conversion Mode. 1 = ADC performs Continuous Conversion Mode. 0 = ADC idle. 5 SCNV: Single Conversion Mode. 1 = ADC performs Single Conversion Mode. Cleared automatically at completion of ADC conversion. 0 = ADC idle. 4:0 INPSEL: Input MUX Select Channels. See Table 3.36. Note: When CCNV and SCNV are both set, the ADC performs in the Continuous Conversion Mode. |
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