HC705E5GRSSLASHD datasheet(22/148 Pages) NXP

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General Description

General Release Specification

MC68HC705E5 — Rev. 1.0

General Description

1.5.3 OSC1 and OSC2

These pins provide control input for an on-chip clock oscillator circuit

which can optionally drive a PLL clock. A crystal, a ceramic resonator, or

an external signal connects to these pins providing a system clock. The

oscillator frequency is two times the internal bus rate if the PLL is not

used.

Crystal

Figure 1-3 (a) shows the recommended circuit for using a crystal. The

crystal and components should be mounted as close as possible to

the input pins to minimize output distortion and startup stabilization

time.

Ceramic Resonator

A ceramic resonator may be used in place of the crystal in

cost-sensitive applications. Figure 1-3 (a) shows the recommended

circuit for using a ceramic resonator. The manufacturer of the

particular ceramic resonator being considered should be consulted

for specific information.

External Clock

An external clock should be applied to the OSC1 input with the OSC2

pin not connected (refer to Figure 1-3 (b)). This setup can be used if

the user does not wish to run the CPU with a 32.768-kHz crystal or

the PLL frequencies are not suitable for the application.

Figure 1-3. Oscillator Connections

OSC1

OSC2

OSC1

OSC2

MCU

EXTERNAL CLOCK

UNCONNECTED

(a) Crystal/Ceramic Resonator

(b) External Clock Source

330 k

Ω

20 M

Ω

32.768 kHz

Oscillator Connections

Connections

33 pF

10 pF

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705E5GRS/D Datasheet(PDF) 22 Page - NXP Semiconductors

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